summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)Author
2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das
Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das
Add support for P2 clock which is sourced from pll3_div2_4_2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4. So fix the clock definitions for P1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it can be reused. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-12clk: renesas: rzg2l: Add multi clock PM supportBiju Das
Add multi clock PM support for cpg driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-08Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: - A handful of fixes for lmk04832 driver - Migrate the basic clk divider to use determine rate ops - Fix modpost build for hisilicon hi3559a driver - Actually set the parent in k210_clk_set_parent() * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: divider: Switch from .round_rate to .determine_rate by default" clk: hisilicon: hi3559a: Drop __init markings everywhere clk: meson: regmap: switch to determine_rate for the dividers clk: divider: Switch from .round_rate to .determine_rate by default clk: divider: Add re-usable determine_rate implementations clk: k210: Fix k210_clk_set_parent() clk: lmk04832: Fix spelling mistakes in dev_err messages and comments clk: lmk04832: fix return value check in lmk04832_probe() clk: stm32mp1: fix missing spin_lock_init()
2021-07-02Merge branch 'akpm' (patches from Andrew)Linus Torvalds
Merge more updates from Andrew Morton: "190 patches. Subsystems affected by this patch series: mm (hugetlb, userfaultfd, vmscan, kconfig, proc, z3fold, zbud, ras, mempolicy, memblock, migration, thp, nommu, kconfig, madvise, memory-hotplug, zswap, zsmalloc, zram, cleanups, kfence, and hmm), procfs, sysctl, misc, core-kernel, lib, lz4, checkpatch, init, kprobes, nilfs2, hfs, signals, exec, kcov, selftests, compress/decompress, and ipc" * emailed patches from Andrew Morton <akpm@linux-foundation.org>: (190 commits) ipc/util.c: use binary search for max_idx ipc/sem.c: use READ_ONCE()/WRITE_ONCE() for use_global_lock ipc: use kmalloc for msg_queue and shmid_kernel ipc sem: use kvmalloc for sem_undo allocation lib/decompressors: remove set but not used variabled 'level' selftests/vm/pkeys: exercise x86 XSAVE init state selftests/vm/pkeys: refill shadow register after implicit kernel write selftests/vm/pkeys: handle negative sys_pkey_alloc() return code selftests/vm/pkeys: fix alloc_random_pkey() to make it really, really random kcov: add __no_sanitize_coverage to fix noinstr for all architectures exec: remove checks in __register_bimfmt() x86: signal: don't do sas_ss_reset() until we are certain that sigframe won't be abandoned hfsplus: report create_date to kstat.btime hfsplus: remove unnecessary oom message nilfs2: remove redundant continue statement in a while-loop kprobes: remove duplicated strong free_insn_page in x86 and s390 init: print out unknown kernel parameters checkpatch: do not complain about positive return values starting with EPOLL checkpatch: improve the indented label test checkpatch: scripts/spdxcheck.py now requires python3 ...
2021-07-01Revert "clk: divider: Switch from .round_rate to .determine_rate by default"Stephen Boyd
This reverts commit db400ac1444b756030249ed4a35e53a68e557b59. We have drivers that are still using the .round_rate ops from here. We could implement both determine_rate and round_rate for these divider ops, but for now let's just kick out the commit that tried to change it and convert various drivers properly. Reported-by: Guenter Roeck <linux@roeck-us.net> Fixes: db400ac1444b ("clk: divider: Switch from .round_rate to .determine_rate by default") Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210702011058.77284-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-01Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round has a diffstat dominated by Qualcomm clk drivers. Honestly though that's just a bunch of data so the diffstat reflects that. Looking beyond that there's just a bunch of updates all around in various clk drivers. Renesas and NXP (for i.MX) are two SoC vendors that have a lot of patches in here. Overall the driver changes look to be mostly enabling more clks and non-critical fixes that we could hold until the next merge window. I'm especially excited about the series from Arnd that graduates clkdev to be the only implementation of clk_get() and clk_put(). That's a good step in the right direction to migreate eveerything over to the common clk framework. Now we don't have to worry about clkdev specific details, they're just part of the clk API now. Core: - clkdev is now the only option, i.e. clk_get()/clk_put() is implemented in only one place in the kernel instead of in drivers/clk/clkdev.c and in architectures that want their own implementation New Drivers: - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs - Qualcomm MDM9607 GCC - Qualcomm SC8180X display clks - Qualcomm SM6125 GCC - Qualcomm SM8250 CAMCC (camera) - Renesas RZ/G2L SoC - Hisilicon hi3559A SoC Updates: - Stop using clock-output-names in ST clk drivers (yay!) - Support secure mode of STM32MP1 SoCs - Improve clock support for Actions S500 SoC - duty cycle setting support on qcom clks - Add TI am33xx spread spectrum clock support - Use determine_rate() for the Amlogic pll ops instead of round_rate() - Restrict Amlogic gp0/1 and audio plls range on g12a/sm1 - Improve Amlogic axg-audio controller error on deferral - Add NNA clocks on Amlogic g12a - Reduce memory footprint of Rockchip PLL rate tables - A fix for the newly added Rockchip rk3568 clk driver - Exported clock for the newly added Rockchip video decoder - Remove audio ipg clock from i.MX8MP - Remove deprecated legacy clock binding for i.MX SCU clock driver - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio, parallel interface) - Add dedicated clock ops for i.MX paralel interface - Different fixes for clocks controlled by ATF on i.MX SoCs - Add A53/A72 frequency scaling support i.MX clk-scu driver - Add special case for DCSS clock on suspend for i.MX clk-scu driver - Add parent save/restore on suspend/resume to i.MX clk-scu driver - Skip runtime PM enablement for CPU clocks in i.MX clk-scu driver - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their bindings - Tegra clk driver no longer deasserts resets on clk_enable as it gets in the way of certain power-up sequences - Fix compile testing for Tegra clk driver - One patch to fix a divider on the Allwinner v3s Audio PLL - Add support for CPU core clock boost modes on Renesas R-Car Gen3 - Add ISPCS (Image Signal Processor) clocks on Renesas R-Car V3U - Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate() and improve support for multiple parents - Switch Renesas RZ/N1 divider clocks to .determine_rate() - Add ZA2 (Audio Clock Generator) clock on Renesas R-Car D3 - Convert ar7 to common clk framework - Convert ralink to common clk framework" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (161 commits) clk: zynqmp: Handle divider specific read only flag clk: zynqmp: Use firmware specific mux clock flags clk: zynqmp: Use firmware specific divider clock flags clk: zynqmp: Use firmware specific common clock flags clk: lmk04832: Use of match table clk: lmk04832: Depend on SPI clk: stm32mp1: new compatible for secure RCC support dt-bindings: clock: stm32mp1 new compatible for secure rcc dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 reset: stm32mp1: remove stm32mp1 reset clk: hisilicon: Add clock driver for hi3559A SoC dt-bindings: Document the hi3559a clock bindings clk: si5341: Add sysfs properties to allow checking/resetting device faults clk: si5341: Add silabs,iovdd-33 property clk: si5341: Add silabs,xaxb-ext-clk property clk: si5341: Allow different output VDD_SEL values clk: si5341: Update initialization magic clk: si5341: Check for input clock presence and PLL lock on startup ...
2021-07-01kernel.h: split out panic and oops helpersAndy Shevchenko
kernel.h is being used as a dump for all kinds of stuff for a long time. Here is the attempt to start cleaning it up by splitting out panic and oops helpers. There are several purposes of doing this: - dropping dependency in bug.h - dropping a loop by moving out panic_notifier.h - unload kernel.h from something which has its own domain At the same time convert users tree-wide to use new headers, although for the time being include new header back to kernel.h to avoid twisted indirected includes for existing users. [akpm@linux-foundation.org: thread_info.h needs limits.h] [andriy.shevchenko@linux.intel.com: ia64 fix] Link: https://lkml.kernel.org/r/20210520130557.55277-1-andriy.shevchenko@linux.intel.com Link: https://lkml.kernel.org/r/20210511074137.33666-1-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Co-developed-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Mike Rapoport <rppt@linux.ibm.com> Acked-by: Corey Minyard <cminyard@mvista.com> Acked-by: Christian Brauner <christian.brauner@ubuntu.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kees Cook <keescook@chromium.org> Acked-by: Wei Liu <wei.liu@kernel.org> Acked-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Sebastian Reichel <sre@kernel.org> Acked-by: Luis Chamberlain <mcgrof@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Helge Deller <deller@gmx.de> # parisc Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-06-30clk: hisilicon: hi3559a: Drop __init markings everywhereStephen Boyd
This driver is a platform driver. The probe function can be called after kernel init, and try to reference kernel memory that has been freed. Drop the __init markings everywhere here to avoid referencing initdata from non-init code. Fixes modpost warnings. Reported-by: kernel test robot <lkp@intel.com> Cc: Dongjiu Geng <gengdongjiu@huawei.com> Fixes: 6c81966107dc ("clk: hisilicon: Add clock driver for hi3559A SoC") Link: https://lore.kernel.org/r/20210630185839.3680834-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: divider: Switch from .round_rate to .determine_rate by defaultMartin Blumenstingl
.determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Switch to a .determine_rate implementation by default so 32-bit systems can benefit from the increased maximum value as well as so we have one fewer user of .round_rate. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-3-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: divider: Add re-usable determine_rate implementationsMartin Blumenstingl
These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. To avoid code-duplication switch over divider_{ro_,}round_rate_parent to use the new divider_{ro_,}determine_rate functions. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: k210: Fix k210_clk_set_parent()Damien Le Moal
In k210_clk_set_parent(), add missing writel() call to update the mux register of a clock to change its parent. This also fixes a compilation warning with clang when compiling with W=1. Fixes: c6ca7616f7d5 ("clk: Add RISC-V Canaan Kendryte K210 clock driver") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210622064502.14841-1-damien.lemoal@wdc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: lmk04832: Fix spelling mistakes in dev_err messages and commentsColin Ian King
There are handful of spelling mistakes in two dev_err error messages and comments. Fix them. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: lmk04832: fix return value check in lmk04832_probe()Wang Hai
In case of error, the function devm_kzalloc() and devm_kcalloc() return NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Hai <wanghai38@huawei.com> Link: https://lore.kernel.org/r/20210630020322.2555946-1-wanghai38@huawei.com Reviewed-by: Liam Beguin <lvb@xiphos.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: stm32mp1: fix missing spin_lock_init()Wang Hai
The driver allocates the spinlock but not initialize it. Use spin_lock_init() on it to initialize it correctly. Fixes: c392df194a2d ("clk: stm32mp1: move RCC reset controller into RCC clock driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Hai <wanghai38@huawei.com> Link: https://lore.kernel.org/r/20210630015824.2555840-1-wanghai38@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-29Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-nextStephen Boyd
- Stop using clock-output-names in ST clk drivers * clk-st: dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: flexgen: embed soc clock outputs within compatible data clk: st: clkgen-pll: remove unused variable of struct clkgen_pll * clk-si: clk: si5341: Add sysfs properties to allow checking/resetting device faults clk: si5341: Add silabs,iovdd-33 property clk: si5341: Add silabs,xaxb-ext-clk property clk: si5341: Allow different output VDD_SEL values clk: si5341: Update initialization magic clk: si5341: Check for input clock presence and PLL lock on startup clk: si5341: Avoid divide errors due to bogus register contents clk: si5341: Wait for DEVICE_READY on startup dt-bindings: clock: clk-si5341: Add new attributes * clk-hisilicon: clk: hisilicon: Add clock driver for hi3559A SoC dt-bindings: Document the hi3559a clock bindings
2021-06-29Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and ↵Stephen Boyd
'clk-ingenic' into clk-next - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs - Support secure mode of STM32MP1 SoCs - Improve clock support for Actions S500 SoC * clk-lmk04832: clk: lmk04832: Use of match table clk: lmk04832: Depend on SPI clk: lmk04832: add support for digital delay clk: add support for the lmk04832 dt-bindings: clock: add ti,lmk04832 bindings * clk-stm: clk: stm32mp1: new compatible for secure RCC support dt-bindings: clock: stm32mp1 new compatible for secure rcc dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 reset: stm32mp1: remove stm32mp1 reset clk: stm32mp1: move RCC reset controller into RCC clock driver clk: stm32mp1: convert to module driver clk: stm32mp1: remove intermediate pll clocks clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock * clk-rohm: clk: bd718xx: Drop BD70528 support * clk-actions: clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC clk: actions: Fix SD clocks factor table on Owl S500 SoC clk: actions: Fix UART clock dividers on Owl S500 SoC * clk-ingenic: clk: ingenic: Add support for the JZ4760 clk: ingenic: Support overriding PLLs M/N/OD calc algorithm clk: ingenic: Remove pll_info.no_bypass_bit clk: ingenic: Read bypass register only when there is one clk: Support bypassing dividers dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles
2021-06-29Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and ↵Stephen Boyd
'clk-socfpga' into clk-next * clk-rockchip: clk: rockchip: export ACLK_VCODEC for RK3036 clk: rockchip: fix rk3568 cpll clk gate bits clk: rockchip: Optimize PLL table memory usage * clk-amlogic: clk: meson: g12a: Add missing NNA source clocks for g12b clk: meson: axg-audio: improve deferral handling clk: meson: g12a: fix gp0 and hifi ranges clk: meson: pll: switch to determine_rate for the PLL ops * clk-yaml: dt-bindings: clock: gpio-mux-clock: Convert to json-schema * clk-zynq: clk: zynqmp: Handle divider specific read only flag clk: zynqmp: Use firmware specific mux clock flags clk: zynqmp: Use firmware specific divider clock flags clk: zynqmp: Use firmware specific common clock flags clk: zynqmp: pll: Remove some dead code clk: zynqmp: fix compile testing without ZYNQMP_FIRMWARE * clk-socfpga: clk: socfpga: clk-pll: Remove unused variable 'rc' clk: agilex/stratix10/n5x: fix how the bypass_reg is handled clk: agilex/stratix10: add support for the 2nd bypass clk: agilex/stratix10: fix bypass representation clk: agilex/stratix10: remove noc_clk
2021-06-29Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and ↵Stephen Boyd
'clk-imx' into clk-next * clk-legacy: clkdev: remove unused clkdev_alloc() interfaces clkdev: remove CONFIG_CLKDEV_LOOKUP m68k: coldfire: remove private clk_get/clk_put m68k: coldfire: use clkdev_lookup on most coldfire mips: ralink: convert to CONFIG_COMMON_CLK mips: ar7: convert to CONFIG_COMMON_CLK mips: ar7: convert to clkdev_lookup * clk-vc5: clk: vc5: fix output disabling when enabling a FOD * clk-allwinner: clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio * clk-nvidia: clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing() clk: tegra: Add stubs needed for compile-testing clk: tegra: Don't deassert reset on enabling clocks clk: tegra: Mark external clocks as not having reset control clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling clk: tegra: Don't allow zero clock rate for PLLs clk: tegra: Halve SCLK rate on Tegra20 clk: tegra: Ensure that PLLU configuration is applied properly clk: tegra: Fix refcounting of gate clocks clk: tegra30: Use 300MHz for video decoder by default * clk-imx: clk: imx8mq: remove SYS PLL 1/2 clock gates clk: imx: scu: Do not enable runtime PM for CPU clks clk: imx: scu: add parent save and restore clk: imx: scu: Only save DC SS clock using non-cached clock rate clk: imx: scu: Add A72 frequency scaling support clk: imx: scu: Add A53 frequency scaling support clk: imx: scu: bypass pi_pll enable status restore clk: imx: scu: detach pd if can't power up clk: imx: scu: bypass cpu clock save and restore clk: imx: scu: add parallel port clock ops clk: imx: scu: add more scu clocks clk: imx: scu: add enet rgmii gpr clocks clk: imx8qm: add clock valid resource checking clk: imx8qxp: add clock valid checking mechnism clk: imx: scu: add gpr clocks support clk: imx: scu: remove legacy scu clock binding support dt-bindings: arm: imx: scu: drop deprecated legacy clock binding dt-bindings: arm: imx: scu: fix naming typo of clk compatible string clk: imx: Remove the audio ipg clock from imx8mp
2021-06-29Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and ↵Stephen Boyd
'clk-ti' into clk-next - duty cycle setting support on qcom clks - qcom MDM9607 GCC - qcom sc8180x display clks - qcom SM6125 GCC - Add TI am33xx spread spectrum clock support * clk-qcom: (22 commits) clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare clk: qcom: Add camera clock controller driver for SM8250 dt-bindings: clock: add QCOM SM8250 camera clock bindings clk: qcom: clk-alpha-pll: add support for zonda pll clk/qcom: Remove unused variables clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocks clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings clk: qcom: Add SM6125 (TRINKET) GCC driver dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver clk: qcom: gcc: Add support for a new frequency for SC7280 clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLK dt-bindings: clock: qcom: rpmcc: Document MSM8226 compatible clk: qcom: dispcc-sm8250: Add EDP clocks clk: qcom: dispcc-sm8250: Add sc8180x support clk: qcom: smd-rpm: De-duplicate identical entries clk: qcom: smd-rpm: Switch to parent_data clk: qcom: Add MDM9607 GCC driver dt-bindings: clock: Add MDM9607 GCC clock bindings clk: qcom: cleanup some dev_err_probe() calls ... * clk-versatile: clk: versatile: Depend on HAS_IOMEM clk: versatile: remove dependency on ARCH_* * clk-renesas: (22 commits) clk: renesas: Add support for R9A07G044 SoC clk: renesas: Add CPG core wrapper for RZ/G2L SoC dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver dt-bindings: clock: Add r9a07g044 CPG Clock Definitions clk: renesas: r8a77995: Add ZA2 clock clk: renesas: cpg-mssr: Make srstclr[] comment block consistent clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions clk: renesas: r9a06g032: Switch to .determine_rate() clk: renesas: div6: Implement range checking clk: renesas: div6: Consider all parents for requested rate clk: renesas: div6: Switch to .determine_rate() clk: renesas: div6: Simplify src mask handling clk: renesas: div6: Use clamp() instead of clamp_t() clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe() clk: renesas: r8a779a0: Add ISPCS clocks clk: renesas: rcar-gen3: Add boost support to Z clocks clk: renesas: rcar-gen3: Add custom clock for PLLs clk: renesas: rcar-gen3: Increase Z clock accuracy clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/ clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate() ... * clk-sifive: clk: analogbits: fix doc warning in wrpll-cln28hpc.c clk: sifive: Fix kernel-doc * clk-ti: drivers: ti: remove redundant error message in adpll.c clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk dt-bindings: clock: ehrpwm: Add support for AM64 specific compatible clk: ti: add am33xx/am43xx spread spectrum clock support ARM: dts: am43xx-clocks: add spread spectrum support ARM: dts: am33xx-clocks: add spread spectrum support dt-bindings: ti: dpll: add spread spectrum support clk: ti: fix typo in routine description
2021-06-28clk: zynqmp: Handle divider specific read only flagRajan Vaja
Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-5-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja
Use ZynqMP specific mux clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-4-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja
Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-3-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific common clock flagsRajan Vaja
Currently firmware passes CCF specific flags to ZynqMP clock driver. So firmware needs to be updated if CCF flags are changed. The firmware should have its own 'flag number space' that is distinct from the common clk framework's 'flag number space'. So define and use ZynqMP specific common clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-2-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: lmk04832: Use of match tableStephen Boyd
Presumably we want to use this match table so add a module device table and set the driver match pointer appropriately. Reported-by: kernel test robot <lkp@intel.com> Cc: Liam Beguin <lvb@xiphos.com> Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Link: https://lore.kernel.org/r/20210629060751.3119453-2-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: lmk04832: Depend on SPIStephen Boyd
This driver depends on SPI. Otherwise compilation fails clk-lmk04832.c:(.text+0x1668): undefined reference to `spi_get_device_id' Reported-by: kernel test robot <lkp@intel.com> Cc: Liam Beguin <lvb@xiphos.com> Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Link: https://lore.kernel.org/r/20210629060751.3119453-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: stm32mp1: new compatible for secure RCC supportGabriel Fernandez
Platform STM32MP1 can be used in configuration where some clock resources cannot be accessed by Linux kernel when executing in non-secure state of the CPU(s). In such configuration, the RCC clock driver must not register clocks it cannot access. They are expected to be registered from another clock driver such as the SCMI clock driver. This change uses specific compatible string "st,stm32mp1-rcc-secure" to specify RCC clock driver configuration where RCC is secure. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-12-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: hisilicon: Add clock driver for hi3559A SoCDongjiu Geng
Add clock drivers for hi3559A SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Link: https://lore.kernel.org/r/1616498973-47067-3-git-send-email-gengdongjiu1@gmail.com [sboyd@kernel.org: Mark arrays static, add __iomem, drop unused array, avoid kfree of devm memory] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add sysfs properties to allow checking/resetting device faultsRobert Hancock
Add sysfs property files to allow viewing the current and latched states of the input present and PLL lock bits, and allow resetting the latched fault state. This allows manual checks or automated userspace polling for faults occurring after initialization. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-10-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,iovdd-33 propertyRobert Hancock
Add a property to allow specifying that the external I2C IO pins are using 3.3V voltage thresholds rather than 1.8V. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-9-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock
Add a property to allow specifying that the device XA/XB pins are used for an external clock input rather than for a clock crystal. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-8-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Allow different output VDD_SEL valuesRobert Hancock
The driver was not previously programming the VDD_SEL values for each output to indicate what external VDDO voltage was used for each. Add ability to specify a regulator supplying the VDDO pin for each output of the device. The voltage of the regulator is used to automatically set the VDD_SEL value appropriately. If no regulator is specified and the chip is being reconfigured, assume 2.5V which appears to be the chip default. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-7-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Update initialization magicRobert Hancock
Update the default register settings to include the VCO_RESET_CALCODE settings (set by the SiLabs ClockBuilder software but not described in the datasheet). Also update part of the initialization sequence to match ClockBuilder and the datasheet. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-6-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock
After initializing the device, wait for it to report that the input clock is present and the PLL has locked before declaring success. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-5-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock
If the Si5341 is being initially programmed and has no stored NVM configuration, some of the register contents may contain unexpected values, such as zeros, which could cause divide by zero errors during driver initialization. Trap errors caused by zero registers or zero clock rates which could result in divide errors later in the code. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-4-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Wait for DEVICE_READY on startupRobert Hancock
The Si5341 datasheet warns that before accessing any other registers, including the PAGE register, we need to wait for the DEVICE_READY register to indicate the device is ready, or the process of the device loading its state from NVM can be corrupted. Wait for DEVICE_READY on startup before continuing initialization. This is done using a raw I2C register read prior to setting up regmap to avoid any potential unwanted automatic PAGE register accesses from regmap at this stage. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-3-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Yu Jiahua <yujiahua1@huawei.com> Link: https://lore.kernel.org/r/20210616034826.37276-1-yujiahua1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-7-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-5-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat
ODF field within the struct clkgen_pll is never used by the driver and can thus be removed. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-2-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: Support bypassing dividersPaul Cercueil
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2024-06-12 02:36:51 +0000