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path: root/drivers/clk
AgeCommit message (Expand)Author
2019-04-11clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5Ding Xiang
2019-04-11clk: zynqmp: fix check for fractional clockMichael Tretter
2019-04-11clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter
2019-04-11clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parentsMichael Tretter
2019-04-11drivers: clk: Update clock driver to handle clock attributeRajan Vaja
2019-04-11drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja
2019-04-11clk: renesas: rcar-gen3: Remove unused variableStephen Boyd
2019-04-10clk: x86: Add system specific quirk to mark clocks as criticalDavid Müller
2019-04-10clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard
2019-04-09clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai
2019-04-08clk: meson: axg-audio: add g12a supportMaxime Jourdan
2019-04-08clk: meson: axg-audio: don't register inputs in the onecell dataJerome Brunet
2019-04-08clk: meson: axg_audio: replace prefix axg by audJerome Brunet
2019-04-04clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara
2019-04-04clk: sunxi-ng: nkmp: Explain why zero width check is neededJernej Skrabec
2019-04-04clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec
2019-04-03clk: imx5: Fix i.MX50 ESDHC clock registersJonathan Neuschäfer
2019-04-03clk: imx5: Fix i.MX50 mainbus clock registersJonathan Neuschäfer
2019-04-03clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec
2019-04-03clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)Jernej Skrabec
2019-04-02clk: renesas: r8a77980: Fix RPC-IF module clock's parentSergei Shtylyov
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi
2019-04-02clk: renesas: r8a774c0: Add Z2 clockSimon Horman
2019-04-02clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara
2019-04-02clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara
2019-04-02clk: renesas: r9a06g032: Add missing PCI USB clockGareth Williams
2019-04-02clk: renesas: r7s9210: Always use readl()Geert Uytterhoeven
2019-04-01clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl
2019-04-01clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl
2019-04-01clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl
2019-04-01clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl
2019-04-01clk: meson-g12a: add video decoder clocksMaxime Jourdan
2019-04-01clk: meson-g12a: add PCIE PLL clocksNeil Armstrong
2019-04-01clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong
2019-04-01clk: meson: g12a: add cpu clocksNeil Armstrong
2019-04-01dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong
2019-04-01dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet
2019-03-29Merge tag 'meson-clk-fixes-for-5.1-v2' of https://github.com/BayLibre/clk-mes...Stephen Boyd
2019-03-29clk: meson: vid-pll-div: remove warning and return 0 on invalid configNeil Armstrong
2019-03-26clk: imx: Remove unused imx_get_clk_hw_fixedAbel Vesa
2019-03-25clk: meson: pll: fix rounding and setting a rate that matches preciselyMartin Blumenstingl
2019-03-22clk: samsung: exynos5410: Add gate clock for ADCKrzysztof Kozlowski
2019-03-21clk: sunxi: Add Kconfig optionsMaxime Ripard