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path: root/drivers/clk
AgeCommit message (Expand)Author
2017-04-05clk: sunxi-ng: mult: Support PLL lock detectionChen-Yu Tsai
2017-04-04Merge branch 'v4.12/clk-drivers' into v4.12/clkKevin Hilman
2017-04-04clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong
2017-04-04clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong
2017-04-04clk: meson: Add support for parameters for specific PLLsNeil Armstrong
2017-04-04clk: meson-gxbb: Add MALI clocksNeil Armstrong
2017-04-04clk: meson-gxbb: Expose GP0 dt-bindings clock idNeil Armstrong
2017-04-04clk: meson-gxbb: Add MALI clock IDSNeil Armstrong
2017-04-04dt-bindings: clk: gxbb: expose i2s output clock gatesJerome Brunet
2017-04-04clk: sunxi-ng: add support for PRCM CCUsIcenowy Zheng
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver
2017-04-04clk: tegra: Propagate clk_out_x rate to parentAlex Frid
2017-04-03clk: stm32f4: fix: exclude values 0 and 1 for PLLQGabriel Fernandez
2017-03-30clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven
2017-03-30clk: renesas: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven
2017-03-30clk: renesas: cpg-mssr: Add support for fixing up clock tablesGeert Uytterhoeven
2017-03-27clk: meson: mpll: correct N2 maximum valueJerome Brunet
2017-03-27clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet
2017-03-27clk: meson: gxbb: mpll: use rw operationJerome Brunet
2017-03-27clk: meson: mpll: add rw operationJerome Brunet
2017-03-27clk: gxbb: put dividers and muxes in tablesJerome Brunet
2017-03-27clk: meson8b: put dividers and muxes in tablesJerome Brunet
2017-03-27clk: meson: add missing const qualifiers on gate arraysJerome Brunet
2017-03-27clk: meson: fix SET_PARM macroJerome Brunet
2017-03-23Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd
2017-03-22clk: rockchip: add pll_wait_lock for pll_enableElaine Zhang
2017-03-22clk: rockchip: rename RK1108 to RV1108Andy Yan
2017-03-21clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0Geert Uytterhoeven
2017-03-21clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven
2017-03-21clk: renesas: r8a7796: Reformat core clock tableGeert Uytterhoeven
2017-03-21clk: renesas: r8a7795: Reformat core clock tableGeert Uytterhoeven
2017-03-21clk: renesas: r8a7796: Correct name of watchdog clockGeert Uytterhoeven
2017-03-21clk: renesas: r8a7795: Correct name of watchdog clockGeert Uytterhoeven
2017-03-21clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACsGeert Uytterhoeven
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver
2017-03-20clk: tegra: Implement reset control resetMikko Perttunen
2017-03-20clk: tegra: Fix disable unused for clocks sharing enable bitPeter De Schrijver
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver
2017-03-20clk: tegra: Add aclkPeter De Schrijver
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver