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Keeping drivers related to HW tracing on ARM, i.e coresight,
under "drivers/coresight" doesn't make sense when other
architectures start rolling out technologies of the same
nature.
As such creating a new "drivers/hwtracing" directory where all
drivers of the same kind can reside, reducing namespace
pollution under "drivers/".
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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>From the TMC TRM, the ETF can be configured as buffer mode, so ETF can
be a sink type.
Signed-off-by: Xia Kaixu <kaixu.xia@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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There are some extra spaces, so just remove them from these lines.
Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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When founding a component that has orphan connections, we should
validate if it match the newly added device. If it does not match,
only then should the @still_orphan flag should be set.
The tested result as follows.
pre:
/sys/bus/coresight/devices # echo 1 > e3c42000.etb/enable_sink
/sys/bus/coresight/devices # echo 1 > e3c7c000.ptm/enable_source
[ 15.527692] Unable to handle kernel NULL pointer dereference at virtual address 00000124
[ 15.555142] pgd = c2294000
[ 15.564226] [00000124] *pgd=3d393831, *pte=00000000, *ppte=00000000
[ 15.585391] Internal error: Oops: 817 [#1] PREEMPT SMP ARM
[ 15.603807] CPU: 0 PID: 144 Comm: sh Not tainted 3.17.0-rc1-12634-g1222fe0-dirty #3
[ 15.629490] task: ed3803c0 ti: c213a000 task.ti: c213a000
[ 15.647627] PC is at coresight_build_paths+0x1c/0x314
[ 15.664579] LR is at coresight_build_paths+0x6c/0x314
[ 15.681526] pc : [<c02da20c>] lr : [<c02da25c>] psr: 20000013
[ 15.681526] sp : c213be88 ip : c02da800 fp : 00000000
[ 15.720023] r10: 00000002 r9 : ed13250c r8 : 00000001
[ 15.737549] r7 : c213bee8 r6 : ffffffea r5 : 00000000 r4 : 00000124
[ 15.759446] r3 : ed216f24 r2 : 00000001 r1 : c213bee8 r0 : 00000000
[ 15.781346] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
post:
/sys/bus/coresight/devices # echo 1 > e3c42000.etb/enable_sink
/sys/bus/coresight/devices # echo 1 > e3c7c000.ptm/enable_source
[ 59.934255] coresight-etb10 e3c42000.etb: ETB enabled
[ 59.951317] coresight-replicator replicator0: REPLICATOR enabled
[ 59.971581] coresight-funnel e3c41000.funnel: FUNNEL inport 0 enabled
[ 59.993334] coresight-etm3x e3c7c000.ptm: ETM tracing enabled
Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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CoreSight components are compliant with the ARM CoreSight
architecture specification and can be connected in various
topologies to suit a particular SoC tracing needs. These trace
components can generally be classified as sources, links and
sinks. Trace data produced by one or more sources flows through
the intermediate links connecting the source to the currently
selected sink.
The CoreSight framework provides an interface for the CoreSight trace
drivers to register themselves with. It's intended to build up a
topological view of the CoreSight components and configure the
correct serie of components on user input via sysfs.
For eg., when enabling a source, the framework builds up a path
consisting of all the components connecting the source to the
currently selected sink(s) and enables all of them.
The framework also supports switching between available sinks
and provides status information to user space applications
through the debugfs interface.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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