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path: root/drivers/crypto/hisilicon/sec2
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2022-03-15hisi_acc_qm: Move VF PCI device IDs to common headerShameer Kolothum
Move the PCI Device IDs of HiSilicon ACC VF devices to a common header and also use a uniform naming convention. This will be useful when we introduce the vfio PCI HiSilicon ACC live migration driver in subsequent patches. Cc: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Longfang Liu <liulongfang@huawei.com> Acked-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h Link: https://lore.kernel.org/r/20220308184902.2242-4-shameerali.kolothum.thodi@huawei.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2022-03-15crypto: hisilicon/qm: Move the QM header to include/linuxShameer Kolothum
Since we are going to introduce VFIO PCI HiSilicon ACC driver for live migration in subsequent patches, move the ACC QM header file to a common include dir. Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Longfang Liu <liulongfang@huawei.com> Acked-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Link: https://lore.kernel.org/r/20220308184902.2242-2-shameerali.kolothum.thodi@huawei.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2022-02-23crypto: hisilicon/sec - fix the aead software fallback for engineKai Ye
Due to the subreq pointer misuse the private context memory. The aead soft crypto occasionally casues the OS panic as setting the 64K page. Here is fix it. Fixes: 6c46a3297bea ("crypto: hisilicon/sec - add fallback tfm...") Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-18crypto: hisilicon/sec - not need to enable sm4 extra mode at HW V3Kai Ye
It is not need to enable sm4 extra mode in at HW V3. Here is fix it. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-18crypto: hisilicon/sec - add the register configuration for HW V3Kai Ye
Added the register configuration of the SVA mode for HW V3. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-01-31crypto: hisilicon/sec - use the correct print formatKai Ye
Use the correct print format. Printing an unsigned int value should use %u instead of %d. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-01-31crypto: hisilicon/sec - fix the CTR mode BD configurationKai Ye
The CTR counter is 32bit rollover default on the BD. But the NIST standard is 128bit rollover. it cause the testing failed, so need to fix the BD configuration. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-01-31crypto: hisilicon/sec - fix the max length of AAD for the CCM modeKai Ye
Fix the maximum length of AAD for the CCM mode due to the hardware limited. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-01-31crypto: hisilicon/sec - add some comments for soft fallbackKai Ye
Modify the print of information that might lead to user misunderstanding. Currently only XTS mode need the fallback tfm when using 192bit key. Others algs not need soft fallback tfm. So others algs can return directly. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-01-31crypto: hisilicon/sec - fixup icv checking enabled on Kunpeng 930Kai Ye
Fixup icv(integrity check value) checking enabled wrong on Kunpeng 930 Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-11-26crypto: hisilicon - modify the value of engine type rateKai Ye
Modify the value of type rate from new QM spec. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - change parameter passing of debugfs functionWeili Qian
To avoid repeatedly obtaining 'qm' from 'filp', parameter passing of debugfs function directly use 'qm' instead of 'filp'. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - support runtime PM for accelerator deviceWeili Qian
Add runtime PM support for Kunpeng930 accelerator device. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon - using 'debugfs_create_file' instead of ↵Weili Qian
'debugfs_create_regset32' The accelerator devices support runtime PM, when device is in suspended, an exception will occur if reading registers. Therefore, this patch uses 'debugfs_create_file' instead of 'debugfs_create_regset32' to create debugfs file, and then the driver can get the device status before reading the register. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon/sec - modify the hardware endian configurationKai Ye
When the endian configuration of the hardware is abnormal, it will cause the SEC engine is faulty that reports empty message. And it will affect the normal function of the hardware. Currently the soft configuration method can't restore the faulty device. The endian needs to be configured according to the system properties. So fix it. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-21crypto: hisilicon/sec - fix the abnormal exiting processKai Ye
Because the algs registration process has added a judgment. So need to add the judgment for the abnormal exiting process. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-08-12crypto: hisilicon - enable sec device clock gatingWeili Qian
Kunpeng930 sec device supports dynamic clock gating. When doing tasks, the algorithm core is opened, and when idle, the algorithm core is closed. This patch enables sec dynamic clock gating by writing hardware registers. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-28crypto: hisilicon/sec - fix the process of disabling sva prefetchingKai Ye
The open interface of the sva prefetching function is distinguish the chip version. But the close interface of the sva prefetching function doesn't distinguish the chip version. As a result, the sva prefetching close operation is also performed on Kunpeng920, those registers are important on Kunpeng920, which eventually leads to abnormal hardware problems. So need to fix it immediately. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-24crypto: hisilicon/sec - Fix spelling mistake "fallbcak" -> "fallback"Colin Ian King
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-17crypto: hisilicon/sec - adds the max shaper type rateKai Ye
The SEC driver support configure each function's QoS in the Host for Kunpeng930. The SEC driver needs to configure the maximum shaper type rate. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - modify the SEC request structureKai Ye
Modify the SEC request structure, combines two common parameters of the SEC request into one parameter. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add hardware integrity check value processKai Ye
Use hardware integrity check value process instead of soft verify process when doing aead decryption. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add fallback tfm supporting for aeadsKai Ye
Add fallback tfm supporting for hisi_sec driver. Due to the Kunpeng920's CCM/GCM algorithm not supports 0 byte src length. So the driver needs to setting the soft fallback aead tfm. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-11crypto: hisilicon/sec - add new algorithm mode for AEADKai Ye
Add new algorithm mode for AEAD: CCM(AES), GCM(AES), CCM(SM4), GCM(SM4). Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - fixup 3des minimum key size declarationKai Ye
Fixup the 3des algorithm minimum key size declaration. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add fallback tfm supporting for XTS modeKai Ye
Add fallback tfm supporting for hisi_sec driver. Due to the hardware not supports 192bit key length when using XTS mode. So the driver needs to setting the soft fallback skcipher tfm for user. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add new skcipher mode for SECKai Ye
Add new skcipher algorithms for Kunpeng930 SEC: OFB(AES), CFB(AES), CTR(AES), OFB(SM4), CFB(SM4), CTR(SM4). Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - driver adapt to new SQEKai Ye
Due to Kunpeng930 adds new SQE data structure, the SEC driver needs to be upgraded. It mainly includes bd parsing process and bd filling process. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-06-03crypto: hisilicon/sec - add new type of SQEKai Ye
Add new type of sqe for Kunpeng930, which is the next generation of SEC accelerator hardware. The hardware adds a new SQE data structure. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-28crypto: hisilicon/qm - support address prefetchingLongfang Liu
Kunpeng930 hardware supports address prefetching to improve performance before doing tasks in SVA scenario. This patch enables this function in device initialization by writing hardware registers. In the process of reset, address prefetching is disabled to avoid the failure of interaction between accelerator device and SMMU. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-23crypto: hisilicon/qm - enable to close master ooo when NFE occursWeili Qian
Kunpeng930 could be able to close master ooo when NFE occurs, which will disable memory accessing from device and execute tasks. This ensures that errors do not spread. This patch enables the hardware to close master ooo when an error occurs by writing hardware registers, and ensures that the driver will not drain qp because the hardware will empty the tasks automatically. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-05-23crypto: hisilicon/qm - adjust order of device error configurationWeili Qian
In order to avoid reporting an exception but the error type is not configured, the driver needs to configure the error type first, and then enable the error interrupt. Before executing the task, hardware error initialization is needed so that the hardware can detect the error in time. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-22crypto: hisilicon - add new error type for SECWeili Qian
Kunpeng930 SEC adds several new hardware error types. This patch enables the new error types and configures the error types as NFE. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-22crypto: hisilicon - dynamic configuration 'err_info'Weili Qian
'err_info' does not support dynamic configuration since it is const type. Therefore, in order to support new error type later, 'err_info' is changed to dynamic configuration. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - fixup checking the 3DES weak keyKai Ye
skcipher: Add a verifying to check whether the triple DES key is weak. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - Fix a module parameter errorLongfang Liu
ctx_q_num is a module parameter set by the user to specify the number of qp queues required to create a ctx. When the number of qp queues allocated by PF or VF is less than the ctx_q_num, an error will be reported when ctx is initialized in kernel mode, which leads to the problem that the registered algorithms cannot be used. Therefore, when PF or VF is initialized, if the number of qp queues is not enough to create a ctx, the kernel mode cannot be used, and there is no need to register the kernel mode algorithms. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/sec - Fixes AES algorithm mode parameter problemLongfang Liu
The input data of the ECB (AES) algorithm needs to be aligned with 16 bytes, and the input data of the XTS (AES) algorithm is at least 16 bytes. Otherwise the SEC hardware will go wrong. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/hpre - delete redundant '\n'Hui Tang
It has newline already by sysfs, so delete redundant '\n' Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - move 'CURRENT_QM' code to qm.cWeili Qian
Since the code related to 'CURRENT_QM' debugfs is exactly same in sec/hpre/zip driver, move 'CURRENT_QM' to qm.c to reduce duplicate code. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - set the total number of queuesWeili Qian
Move the configuration of the total number of queues 'ctrl_qp_num' from sec2/hpre/zip to qm.c. And get the total number of queues from the hardware register for Kunpeng930. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon - fix the check on dma addressHui Tang
System may be able to get physical address of zero if not reserved by firmware. The dma address obtained by 'dma_alloc_coherent' is valid, since already checking cpu va before, so do not check again. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes some driver coding styleLongfang Liu
cleanup static check errors for SEC Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes some coding styleLongfang Liu
1.delete the original complex method of obtaining the current device and replace it with the initialized device pointer. 2.fixes some coding style Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes a printing errorLongfang Liu
When the log is output here, the device has not been initialized yet. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-13crypto: hisilicon/hpre - add version adapt to new algorithmsMeng Yu
A new generation of accelerator Kunpeng930 has appeared, and the corresponding driver needs to be updated to support some new algorithms of Kunpeng930. To be compatible with Kunpeng920, we add parameter 'struct hisi_qm *qm' to sec_algs_(un)register to identify the chip's version. Signed-off-by: Meng Yu <yumeng18@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - do not reset hardware when CE happensWeili Qian
There is no need to reset hardware when Corrected Error(CE) happens. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - removing driver after resetWeili Qian
Add waiting logic for resetting as removing driver, otherwise call trace will occur due to releasing resource. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon - PASID fixed on Kunpeng 930Weili Qian
Enable PASID by setting 'sqc' and 'cqc' pasid bits per queue in Kunpeng 930. For Kunpeng 920, PASID is effective for all queues once set in SVA scenarios. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-14crypto: hisilicon/sec - register SEC device to uacceKai Ye
Register SEC device to uacce framework for user space. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-20crypto: sha - split sha.h into sha1.h and sha2.hEric Biggers
Currently <crypto/sha.h> contains declarations for both SHA-1 and SHA-2, and <crypto/sha3.h> contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split <crypto/sha.h> into two headers <crypto/sha1.h> and <crypto/sha2.h>, and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by: Eric Biggers <ebiggers@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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