| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-06-15 | cxl/core: Add cxl-bus driver infrastructure | Dan Williams |
| 2021-06-12 | cxl/component_regs: Fix offset | Ben Widawsky |
| 2021-06-12 | cxl/hdm: Fix decoder count calculation | Ben Widawsky |
| 2021-06-09 | cxl/acpi: Introduce cxl_decoder objects | Dan Williams |
| 2021-06-09 | cxl/acpi: Add downstream port data to cxl_port instances | Dan Williams |
| 2021-06-09 | cxl/acpi: Introduce the root of a cxl_port topology | Dan Williams |
| 2021-06-05 | cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *' | Dan Williams |
| 2021-06-05 | cxl/pci: Add HDM decoder capabilities | Ben Widawsky |
| 2021-06-05 | cxl/pci: Reserve individual register block regions | Ira Weiny |
| 2021-06-05 | cxl/pci: Map registers based on capabilities | Ira Weiny |
| 2021-05-26 | cxl/mem: Demarcate vendor specific capability IDs | Ben Widawsky |
| 2021-05-14 | cxl/core: Refactor CXL register lookup for bridge reuse | Dan Williams |
| 2021-05-14 | cxl/core: Rename bus.c to core.c | Dan Williams |
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
| summaryrefslogtreecommitdiff |