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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams
2023-06-25cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams
2023-06-25cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron
2023-05-30cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams
2023-04-04cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams
2023-04-04cxl/hdm: Skip emulation when driver manages mem_enableDan Williams
2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams
2023-02-10tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams
2023-02-10cxl/region: Add region autodiscoveryDan Williams
2023-02-10cxl/region: Add a mode attribute for regionsDan Williams
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso
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