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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky
2022-02-08cxl/core/port: Add switch port enumerationDan Williams
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams
2022-02-08cxl: Prove CXL lockingDan Williams
2022-02-08cxl/core: Track port depthBen Widawsky
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky
2022-01-04cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor
2021-11-15cxl/pmem: Fix module reload vs workqueue stateDan Williams
2021-11-08Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams
2021-09-25cxl/core: Replace unions with struct_group()Kees Cook
2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams
2021-09-21cxl/bus: Populate the target list at decoder createDan Williams
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams
2021-09-21cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams
2021-08-06cxl/pci: Simplify register setupBen Widawsky
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams
2021-05-14cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams
2021-05-14cxl/mem: Move some definitions to mem.hDan Williams
2021-02-16cxl/mem: Enable commands via CELBen Widawsky
2021-02-16cxl/mem: Register CXL memX devicesDan Williams
2021-02-16cxl/mem: Find device capabilitiesBen Widawsky
generated by cgit (git 2.34.1) at 2024-06-15 12:42:20 +0000