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path: root/drivers/dma/dma-axi-dmac.c
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2019-01-20dmaengine: axi-dmac: Use struct_size() in kzalloc()Gustavo A. R. Silva
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; void *entry[]; }; instance = kzalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL); This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-05-02dmaengine: axi-dmac: Request IRQ with IRQF_SHAREDMoritz Fischer
Request IRQ with IRQF_SHARED flag to enable setups with multiple instances of the core sharing a single IRQ line. This works out since the IRQ handler already checks if there is an actual IRQ pending and returns IRQ_NONE otherwise. Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2017-09-17dmaengine: axi-dmac: Fix software cyclic modeLars-Peter Clausen
When running in software cyclic mode the driver currently does not go back to the first segment once the last segment has been reached. Effectively making the transfer non-cyclic. Fix this by going back to the first segment once the last segment has been reached for cyclic transfers. Special care need to be taken to avoid a segment from being submitted multiple times concurrently, which could happen for transfers with a number of segments that is smaller than the DMA controller's internal queue. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-17dmaengine: axi-dmac: Only use hardware cyclic mode for single segment transfersLars-Peter Clausen
In hardware cyclic mode the submitted segment is repeated. This means hardware cyclic mode can only be used if the transfer has a single segment. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-01dmaengine: axi-dmac: Return IRQ_NONE if no IRQs are pendingLars-Peter Clausen
Return IRQ_NONE in the interrupt handler when it is called but no IRQs are pending. This allows the system to recover in case of an interrupt storm e.g. due to a wrong interrupt configuration setup. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-01dmaengine: axi-dmac: Propagate errors from platform_get_irq()Lars-Peter Clausen
Propagate errors returned by platform_get_irq() to the driver core. This will enable proper probe deferring for the driver in case the IRQ provider has not been registered yet. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-01dmaengine: axi-dmac: Add MODULE_DEVICE_TABLE()Lars-Peter Clausen
Add MODULE_DEVICE_TABLE() for the axi-dmac driver. This allows the driver to be loaded on demand when built as a module. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-11-16dmaengine: axi_dmac: Add synchronization supportLars-Peter Clausen
Implement the new device_synchronize() callback to allow proper synchronization when stopping a channel. Since the driver already makes sure that no new complete callbacks are scheduled after the device_terminate_all() callback has been called, all left to do in the device_synchronize() callback is to wait for all currently running complete callbacks to finish. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-23dmaengine: Add support for the Analog Devices AXI-DMAC DMA controllerLars-Peter Clausen
Add support for the Analog Devices AXI-DMAC DMA controller. This controller is a soft peripheral that can be instantiated in a FPGA and is often used in Analog Devices' reference designs for FPGA platforms. The peripheral has various configuration options that can be selected at synthesis time and influence the supported features of the instantiated peripheral, those options are represented as device-tree properties to allow the driver to behave accordingly. The peripheral has a zero latency architecture, which means it is possible to switch from one to the next descriptor without any delay. This is archived by having a internal queue which can hold multiple descriptors. The driver supports this, which means it will submit new descriptors directly to the hardware until the queue is full and not wait for a descriptor to complete before the next one is submitted. Interrupts are used for the descriptor queue flow control. Currently the driver supports SG, cyclic and interleaved slave DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>