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path: root/drivers/fpga/zynq-fpga.c
AgeCommit message (Expand)Author
2020-03-30fpga: zynq: Remove clk_get error message for probe deferShubhrajyoti Datta
2019-10-04fpga: Remove dev_err() usage after platform_get_irq()Stephen Boyd
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285Thomas Gleixner
2018-11-11zynq-fpga: Only route PR via PCAP when requiredMike Looijmans
2018-10-16fpga: mgr: add devm_fpga_mgr_createAlan Tull
2018-05-25fpga: manager: change api, don't use drvdataAlan Tull
2017-03-17fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer
2017-02-10fpga zynq: Use the scatterlist interfaceJason Gunthorpe
2017-02-10fpga zynq: Check the bitstream for validityJason Gunthorpe
2017-02-10fpga zynq: Check for errors after completing DMAJason Gunthorpe
2016-11-29fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe
2016-11-29fpga zynq: Remove priv->devJason Gunthorpe
2016-11-29fpga zynq: Add missing \n to messagesJason Gunthorpe
2016-11-10fpga-mgr: add fpga image information structAlan Tull
2015-10-23fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer
2015-10-23fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer
2015-10-23fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer
2015-10-17fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer