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path: root/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
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2020-01-22drm/amdgpu: remove unnecessary conversion to boolNirmoy Das
Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhubchangzhu
SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: refine query function of mmhub EDC counter in vg20Dennis Li
Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07drm/amdgpu: remove duplicated include from mmhub_v1_0.cYueHaibing
Remove duplicated include. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-16drm/amdgpu: Disable retry faults in VMID0Felix Kuehling
There is no point retrying page faults in VMID0. Those faults are always fatal. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-13drm/amdgpu/mmhub: switch to amdgpu_mmhub_ras_late_init helper functionHawking Zhang
amdgpu_mmhub_ras_late_init is used to init mmhub specfic ras debugfs/sysfs node and mmhub specific interrupt handler. It can be shared among mmhub generations Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-13drm/amdgpu: set ip specific ras interface pointer to NULL after free itHawking Zhang
to prevent access to dangling pointers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-13drm/amdgpu: fix memory leak when ras is not supported on specific ip blockHawking Zhang
free ras_if if ras is not supported Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-13drm/amdgpu: add mmhub ras_late_init callback function (v2)Hawking Zhang
The function will be called in late init phase to do mmhub ras init v2: check ras_late_init function pointer before invoking the function Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu/mmhub1: set mmhub clock gating for rnPrike Liang
setup mmhub clockgating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: implement querying ras error count for mmhubTao Zhou
get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-12drm/amdgpu: split athub clock gating from mmhubLe Ma
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-12drm/amdgpu: add amdgpu_mmhub_funcs definitionTao Zhou
add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: cleanup vega10 SRIOV code pathMonk Liu
we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub numberLe Ma
The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amdkfd: Consistently apply noretry settingFelix Kuehling
Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König <Christian.Koenig@amd.com> CC: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by : Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-24drm/amdgpu: Skip setting some regs under Vega10 VFTrigger Huang
For Vega10 SR-IOV VF, skip setting some regs due to: 1, host will program them 2, avoid VF register programming violations Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-08Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm updates from Dave Airlie: "This has two exciting community drivers for ARM Mali accelerators. Since ARM has never been open source friendly on the GPU side of the house, the community has had to create open source drivers for the Mali GPUs. Lima covers the older t4xx and panfrost the newer 6xx/7xx series. Well done to all involved and hopefully this will help ARM head in the right direction. There is also now the ability if you don't have any of the legacy drivers enabled (pre-KMS) to remove all the pre-KMS support code from the core drm, this saves 10% or so in codesize on my machine. i915 also enable Icelake/Elkhart Lake Gen11 GPUs by default, vboxvideo moves out of staging. There are also some rcar-du patches which crossover with media tree but all should be acked by Mauro. Summary: uapi changes: - Colorspace connector property - fourcc - new YUV formts - timeline sync objects initially merged - expose FB_DAMAGE_CLIPS to atomic userspace new drivers: - vboxvideo: moved out of staging - aspeed: ASPEED SoC BMC chip display support - lima: ARM Mali4xx GPU acceleration driver support - panfrost: ARM Mali6xx/7xx Midgard/Bitfrost acceleration driver support core: - component helper docs - unplugging fixes - devm device init - MIPI/DSI rate control - shmem backed gem objects - connector, display_info, edid_quirks cleanups - dma_buf fence chain support - 64-bit dma-fence seqno comparison fixes - move initial fb config code to core - gem fence array helpers for Lima - ability to remove legacy support code if no drivers requires it (removes 10% of drm.ko size) - lease fixes ttm: - unified DRM_FILE_PAGE_OFFSET handling - Account for kernel allocations in kernel zone only panel: - OSD070T1718-19TS panel support - panel-tpo-td028ttec1 backlight support - Ronbo RB070D30 MIPI/DSI - Feiyang FY07024DI26A30-D MIPI-DSI panel - Rocktech jh057n00900 MIPI-DSI panel i915: - Comet Lake (Gen9) PCI IDs - Updated Icelake PCI IDs - Elkhartlake (Gen11) support - DP MST property addtions - plane and watermark fixes - Icelake port sync and VEBOX disable fixes - struct_mutex usage reduction - Icelake gamma fix - GuC reset fixes - make mmap more asynchronous - sound display power well race fixes - DDI/MIPI-DSI clocks for Icelake - Icelake RPS frequency changing support - Icelake workarounds amdgpu: - Use HMM for userptr - vega20 experimental smu11 support - RAS support for vega20 - BACO support for vega12 + fixes for vega20 - reworked IH interrupt handling - amdkfd RAS support - Freesync improvements - initial timeline sync object support - DC Z ordering fixes - NV12 planes support - colorspace properties for planes= - eDP opts if eDP already initialized nouveau: - misc fixes etnaviv: - misc fixes msm: - GPU zap shader support expansion - robustness ABI addition exynos: - Logging cleanups tegra: - Shared reset fix - CPU cache maintenance fix cirrus: - driver rewritten using simple helpers meson: - G12A support vmwgfx: - Resource dirtying management improvements - Userspace logging improvements virtio: - PRIME fixes rockchip: - rk3066 hdmi support sun4i: - DSI burst mode support vc4: - load tracker to detect underflow v3d: - v3d v4.2 support malidp: - initial Mali D71 support in komeda driver tfp410: - omap related improvement omapdrm: - drm bridge/panel support - drop some omap specific panels rcar-du: - Display writeback support" * tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm: (1507 commits) drm/msm/a6xx: No zap shader is not an error drm/cma-helper: Fix drm_gem_cma_free_object() drm: Fix timestamp docs for variable refresh properties. drm/komeda: Mark the local functions as static drm/komeda: Fixed warning: Function parameter or member not described drm/komeda: Expose bus_width to Komeda-CORE drm/komeda: Add sysfs attribute: core_id and config_id drm: add non-desktop quirk for Valve HMDs drm/panfrost: Show stored feature registers drm/panfrost: Don't scream about deferred probe drm/panfrost: Disable PM on probe failure drm/panfrost: Set DMA masks earlier drm/panfrost: Add sanity checks to submit IOCTL drm/etnaviv: initialize idle mask before querying the HW db drm: introduce a capability flag for syncobj timeline support drm: report consistent errors when checking syncobj capibility drm/nouveau/nouveau: forward error generated while resuming objects tree drm/nouveau/fb/ramgk104: fix spelling mistake "sucessfully" -> "successfully" drm/nouveau/i2c: Disable i2c bus access after ->fini() drm/nouveau: Remove duplicate ACPI_VIDEO_NOTIFY_PROBE definition ...
2019-04-12drm/amdgpu/gmc9: fix VM_L2_CNTL3 programmingAlex Deucher
Got accidently dropped when 2+1 level support was added. Fixes: 6a42fd6fbf534096 ("drm/amdgpu: implement 2+1 PD support for Raven v3") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2019-03-20drm/amdgpu: re-enable retry faultsChristian König
Now that we have re-reoute faults to the other IH ring we can enable retries again. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-19drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0Yong Zhao
This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-19Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next New features for 4.21: amdgpu: - Support for SDMA paging queue on vega - Put compute EOP buffers into vram for better performance - Share more code with amdkfd - Support for scanout with DCC on gfx9 - Initial kerneldoc for DC - Updated SMU firmware support for gfx8 chips - Rework CSA handling for eventual support for preemption - XGMI PSP support - Clean up RLC handling - Enable GPU reset by default on VI, SOC15 dGPUs - Ring and IB test cleanups amdkfd: - Share more code with amdgpu ttm: - Move global init out of the drivers scheduler: - Track if schedulers are ready for work - Timeout/fault handling changes to facilitate GPU recovery Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114165113.3751-1-alexander.deucher@amd.com
2018-11-12drm/amdgpu: set system aperture to cover whole FB regionshaoyunl
In XGMI configuration, the FB region covers vram region from peer device, adjust system aperture to cover all of them Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to useYong Zhao
kfd has the same need to set the VM page table base register, so expose them for kfd to use for better maintainability. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-24drm/amdgpu: Fix null point errorRex Zhu
need to check adev->powerplay.pp_funcs first, becasue from AI, the smu ip can be disabled by user, and the pp_handle is null in this case. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: fix the page fault of raven2Huang Rui
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amdgpu: simplify Raven, Raven2, and Picasso handlingAlex Deucher
Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amdgpu: fix the VM fault while write at the top of the invisible vramHuang Rui
Raven2 has a HW issue that it is unable to use the vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system aperture high address to get rid of the VM fault and hardware hang. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amdgpu: enable mmhub power gatingKenneth Feng
Remove some functions due to the design change. All the mmhub power gating sequence is moved to smu fw.Driver sends the message to enable mmhub powergating.We can also skip the fw version check since the old fw version is in a very early stage and we don't use that fw for release. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amdgpu: add clockgating support for picassoLikun Gao
Treat it the same as raven for now. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amdgpu/gmc9: Adjust GART and AGP location with xgmi offset (v2)Alex Deucher
On hives with xgmi enabled, the fb_location aperture is a size which defines the total framebuffer size of all nodes in the hive. Each GPU in the hive has the same view via the fb_location aperture. GPU0 starts at offset (0 * segment size), GPU1 starts at offset (1 * segment size), etc. For access to local vram on each GPU, we need to take this offset into account. This including on setting up GPUVM page table and GART table v2: squash in "drm/amdgpu: Init correct fb region for none XGMI configuration" Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Slava Abramov <slava.abramov@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Huang Rui <ray.huang@amd.com>
2018-09-10drm/amdgpu: enable AGP aperture for GMC9 v2Christian König
Enable the old AGP aperture to avoid GART mappings. v2: don't enable it for SRIOV Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: add amdgpu_gmc_pd_addr helperChristian König
Add a helper to get the root PD address and remove the workarounds from the GMC9 code for that. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: remove gart.table_addrChristian König
We can easily figure out the address on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smuRex Zhu
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhubRex Zhu
In order to keep consistent with powergate_uvd/vce. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17drm/amdgpu/mmhub: Add clockgating support for vega20Feifei Xu
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21drm/amdgpu/mmhub: add clockgating support for vega12Alex Deucher
Treat it the same as vega10 for now. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2018-02-26drm/amdgpu: use the TTM dummy page instead of allocating oneChristian König
We have a global dummy page in TTM, use that one instead of allocating a new one. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: add mmhub powergating set by smuEric Huang
PSP will disable legacy mmhub PG setting that is programming registers, and drive will use SMC message to set it up. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.hChristian König
And rename it to amdgpu_gmc as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: Update MMHUB power gating register settingsYong Zhao
The new register settings are needed to fix a tlb invalidation issue when MMHUB power gating is turned on for Raven. Signed-off-by: Yong Zhao <yong.zhao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-18drm/amdgpu: implement 2+1 PD support for Raven v3Christian König
Instead of falling back to 2 level and very limited address space use 2+1 PD support and 128TB + 512GB of virtual address space. v2: cleanup defines, rebase on top of level enum v3: fix inverted check in hardware setup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-08drm/admgpu: Reduce the usage of soc15ip.hShaoyun Liu
Remove the header where it's not used. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 header files.Feifei Xu
Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 mmhub header files.Feifei Xu
Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 athub header files.Feifei Xu
Cleanup asic_reg/vega10/ATHUB folder,remove unused files. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu:halt when vm faultMonk Liu
only with this way we can debug the VMC page fault issue Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-13drivers:gpu:Use ARRAY_SIZE() for the size calculation of the array.Allen Pais
Signed-off-by: Allen Pais <allen.lkml@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-29drm/amd/amdgpu: fix BANK_SELECT on Vega10 (v2)Roger He
BANK_SELECT should always be FRAGMENT_SIZE + 3 due to 8-entry (2^3) per cache line in L2 TLB for Vega10. v2: agd: fix warning Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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