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path: root/drivers/gpu/drm/amd/amdgpu
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2018-10-10drm/amdgpu: fix CPDMA hang in PRT modeTao Zhou
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX Affected ASICs: Vega10 Vega12 Raven Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Tested-by: Yukun.Li <yukun1.li@amd.com> Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Change VI gfx/sdma/smu init sequenceRex Zhu
initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Add fw load in gfx_v8 and sdma_v3Rex Zhu
gfx and sdma can be initialized before smu. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Don't reallocate ucode bo when suspendRex Zhu
driver don't release the ucode memory when suspend. so don't need to allocate bo when resume back. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Remove FW_LOAD_DIRECT type support on VIRex Zhu
AMDGPU_FW_LOAD_DIRECT is used for bring up. Now it don't work any more. so remove the support. v2: Add warning message if user select AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu/vcn:Correct VCN cache window definitionJames Zhu
Correct VCN cache window definition. The old one is reused from UVD, and it is not fully correct. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu/vcn:Replace value with defined macroJames Zhu
Replace value with defined macro to make code more readable Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu/vcn:fix dpg pause mode hang issueJames Zhu
Use mmUVD_SCRATCH2 tracking decode write point. It will help avoid dpg pause mode hang issue. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu/vcn:Remove unused codeJames Zhu
The following WREG32_SOC15_DPG_MODE will overwrite register mmUVD_CGC_CTRL. This code can be removed. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.cChristian König
Adding a second irq source because of a different src_id is actually a bug. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: fix AGP location with VRAM at 0x0Christian König
That also simplifies handling quite a bit. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: remove the intterupt handling for the KIQ eventsShirish S
[Why] 1. we never submit IBs to the KIQ 2. there seems to be ~500ms delay during amdgpu resume spent in KIQ, hence pointing toward interrupts are not working correctly. [How] remove interrupt handling for KIQ. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>i Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: skip IB tests for KIQ in generalPratik Vishwakarma
[Why] 1. We never submit IBs to KIQ. 2. Ring test pass without KIQ's ring also. 3. By skipping we see an improvement of around 500ms in the amdgpu's resume time. [How] skip IB tests for KIQ ring type. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Move gfx flag in_suspend to adevRex Zhu
Move in_suspend flag to adev from gfx, so can be used in other ip blocks, also keep consistent with gpu_in_reset flag. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Drop dead define in amdgpu.hRex Zhu
the struct was not in use any more. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Always enable fan sensors for readRex Zhu
don't need to set fan1_enable to read fan sensors. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Disable sysfs pwm1 if not in manual fan controlRex Zhu
Following lm-sensors 3.0.0, Only enable pwm1 sysfs when fan control mode(pwm1_enable) in manual Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Add fan RPM setting via sysfsRex Zhu
Add fan1_target for get/set fan speed in RPM unit Add fan1_min/fan1_max for get min, max fan speed in RPM unit Add fan1_enable to enable/disable the fan1 sensor v3: drop the hardcode value of min/max rpm in comments pointed out by Alex. v2: query the min/max rpm gpu support instand of hardcode value. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msgRex Zhu
1. make uvd_v7_0_enc_get_destroy_msg static 2. drop a function variable that always true Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Move out power up/down sdma out of smuRex Zhu
smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gatingRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amd/powerplay: helper interfaces for MGPU fan boost featureEvan Quan
MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: added AMD GPU instance counting V2Evan Quan
Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: change Raven always on CUs to 4Evan Quan
For Vega10 and Vega20, the always on CUs are 12. For Raven, it's 4. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amdgpu: added vega20 LBPW support v2Evan Quan
Enable LBPW support on vega20. v2: squash in warning fix (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-05drm: Remove defunct dma_buf_kmap stubsChris Wilson
Since commit 09ea0dfbf972 ("dma-buf: make map_atomic and map function pointers optional"), we no longer need to provide stub no-op functions as the core now provides them directly. References: 09ea0dfbf972 ("dma-buf: make map_atomic and map function pointers optional") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180807174748.4503-1-chris@chris-wilson.co.uk
2018-10-04BackMerge v4.19-rc6 into drm-nextDave Airlie
I have some pulls based on rc6, and I prefer to have an explicit backmerge. Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-09-27drm/amdgpu: Fix vce work queue was not cancelled when suspendRex Zhu
The vce cancel_delayed_work_sync never be called. driver call the function in error path. This caused the A+A suspend hang when runtime pm enebled. As we will visit the smu in the idle queue. this will cause smu hang because the dgpu has been suspend, and the dgpu also will be waked up. As the smu has been hang, so the dgpu resume will failed. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-09-26drm/amdgpu/vcn: whitespace cleanupAlex Deucher
Fix some indentation issues. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu/soc15: fix warnings in register macroAlex Deucher
expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Enable DPG mode on PCOJames Zhu
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Add DPG pause mode supportJames Zhu
Add functions to support VCN DPG pause mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Add DPG pause stateJames Zhu
Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Add DPG mode support for vcn 1.0James Zhu
Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Add DPG mode read/write macroJames Zhu
Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib testJames Zhu
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: move more defines into amdgpu_irq.hChristian König
Everything that isn't related to the IH ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: move more interrupt processing into amdgpu_irq.cChristian König
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Move fence SW fallback warning v3Andrey Grodzovsky
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: cleanup amdgpu_ih.cChristian König
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: make function pointers mandatoryChristian König
We always want those to be setup correctly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: drop extra newline in amdgpu_iv traceChristian König
That is superflous here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: fix the page fault of raven2Huang Rui
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Remove redundant code in gfx_v8_0.cRex Zhu
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hang Zhou <hang.zhou@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Halt rlc/cp in rlc_safe_modeRex Zhu
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hang Zhou <hang.zhou@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Refine function nameRex Zhu
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2Andrey Grodzovsky
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian Konig <Christian.Koenig@amd.com> Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu: Add vega20 support on kfd probeShaoyun Liu
Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2018-09-26drm/amd: Interface change to support 64 bit page_table_baseShaoyun Liu
amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10Emily Deng
Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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