summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display
AgeCommit message (Collapse)Author
2021-04-09drm/amd/display: add mod hdcp interface for supporting encryption state queryWenjing Liu
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: define mod_hdcp_display_disable_option structWenjing Liu
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: enable DP DSC Compliance automationQingqing Zhuo
[Why] Color depth data is not parsed during test requests. [How] Update display color depth according to color depth request from the test equipment. Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Guard ASSR with internal display flagStylon Wang
[Why] ASSR enabling only considers capability declared in DPCD. We also need to check whether the connector is internal. [How] ASSR enabling need to check both DPCD capability and internal display flag. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Fix static checker warnings on tracebuff_fbLeo (Hanghong) Ma
[Why] Static analysis on linux-next has found a potential null pointer dereference; [How] Refactor the function, add ASSERT and remove the unnecessary check. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Add refresh rate traceRodrigo Siqueira
When we have to debug VRR issues, we usually want to know the current refresh rate; for this reason, it is handy to have a way to check in real-time the refresh rate value. This commit introduces a kernel trace that can provide such information. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: BIOS LTTPR Caps InterfaceWesley Chalmers
[WHY] Some platforms will have LTTPR capabilities forced on by VBIOS flags; the functions added here will access those flags. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Fix black screen with scaled modes on some eDP panelsNikola Cornij
[why] This was a regression introduced by commit: drm/amd/display: Skip modeset for front porch change Due to the change how timing parameters were set, scaled modes would cause a black screen on some eDP panels. Would probably apply to other displays (i.e. even non-eDP) that only have scaled modes, but such case is not that usual for external displays. [how] Pick up crtc frame dimensions when programming the timing unless it's FreeSync video mode. Fixes: 6f59f229f8ed7a ("drm/amd/display: Skip modeset for front porch change") Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: check fb of primary planeSefa Eyeoglu
Sometimes the primary plane might not be initialized (yet), which causes dm_check_crtc_cursor to divide by zero. Apparently a weird state before a S3-suspend causes the aforementioned divide-by-zero error when resuming from S3. This was explained in bug 212293 on Bugzilla. To avoid this divide-by-zero error we check if the primary plane's fb isn't NULL. If it's NULL the src_w and src_h attributes will be 0, which would cause a divide-by-zero. This fixes Bugzilla report 212293 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=212293 Fixes: 12f4849a1cfd69f3 ("drm/amd/display: check cursor scaling") Reviewed-by: Simon Ser <contact@emersion.fr> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Sefa Eyeoglu <contact@scrumplex.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Allow idle optimization based on vblank.Bindu Ramamurthy
[Why] idle optimization was being disabled after commit. [How] check vblank count for display off and enable idle optimization based on this count. Also,check added to ensure vblank count does not decrement, when count reaches 0. Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: Ensure that the modifier requested is supported by plane.Mark Yacoub
On initializing the framebuffer, call drm_any_plane_has_format to do a check if the modifier is supported. drm_any_plane_has_format calls dm_plane_format_mod_supported which is extended to validate that the modifier is on the list of the plane's supported modifiers. The bug was caught using igt-gpu-tools test: kms_addfb_basic.addfb25-bad-modifier Tested on ChromeOS Zork by turning on the display, running an overlay test, and running a YT video. === Changes from v1 === Explicitly handle DRM_FORMAT_MOD_INVALID modifier. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Mark Yacoub <markyacoub@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Removing unused code from dmub_cmd.hAnson Jacob
Removing code that is not used at the moment. Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Use appropriate DRM_DEBUG_... levelLuben Tuikov
Convert IRQ-based prints from DRM_DEBUG_DRIVER to the appropriate DRM log type, since IRQ-based prints drown out the rest of the driver's DRM_DEBUG_DRIVER messages. v2: Update as per feedback to fine-tune for each type of DRM log level. Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/pm: make DAL communicate with SMU through unified interfacesEvan Quan
No need to have special handlings for swSMU supported ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu/display: fix memory leak for dimgrey cavefishAlex Deucher
We need to clean up the dcn3 clk_mgr. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: 3.2.128Aric Cyr
This version brings along following fixes: - Populate socclk entries for dcn2.1 - hide VGH asic specific structs - Add kernel doc to crc_rd_wrk field - revert max lb lines change - Log DMCUB trace buffer events - Fix debugfs link_settings entry - revert max lb use by default for n10 - Deallocate IRQ handlers on amdgpu_dm_irq_fini - Fixed Clock Recovery Sequence - Fix UBSAN: shift-out-of-bounds warning - [FW Promotion] Release 0.0.57 - Change input parameter for set_drr - Use pwrseq instance to determine eDP instance Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Use pwrseq instance to determine eDP instanceJake Wang
[Why & How] Link index doesn't always correspond to the appropriate eDP instance. We can assume lower link index is a lower eDP instance and set panel control instance accordingly. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Change input parameter for set_drrAlvin Lee
[Why] Change set_drr to pass in the entire dc_crtc_timing_adjust structure instead of passing in the parameters individually. This is to more easily pass in required parameters in the adjust structure when it gets updated. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: [FW Promotion] Release 0.0.57Anthony Koo
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Fix UBSAN: shift-out-of-bounds warningAnson Jacob
[Why] On NAVI14 CONFIG_UBSAN reported shift-out-of-bounds at display_rq_dlg_calc_20v2.c:304:38 rq_param->misc.rq_c.blk256_height is 0 when chroma(*_c) is invalid. dml_log2 returns -1023 for log2(0), although log2(0) is undefined. Which ended up as: rq_param->dlg.rq_c.swath_height = 1 << -1023 [How] Fix applied on all dml versions. 1. Ensure dml_log2 is only called if the argument is greater than 0. 2. Subtract req128_l/req128_c from log2_swath_height_l/log2_swath_height_c only when it is greater than 0. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Fixed Clock Recovery SequenceDavid Galiffi
[Why] When performing clock recovery, if a pre-emphasis adjustment is requested, but voltage swing remains constant, the the retry counter will not be reset. This can lead to prematurely failing link training. [How] Reset the clock recovery retry counter if an adjustment is requested for either voltage swing or pre-emphasis. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Calvin Hou <Calvin.Hou@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_finiVictor Lu
[why] The amdgpu_dm IRQ handlers are not freed during the IRQ teardown. [how] Add function to deallocate IRQ handlers on amdgpu_dm_irq_fini step. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: revert max lb use by default for n10Dmytro Laktyushkin
This is causing a pstate change underflow regression for unknown reason Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Fix debugfs link_settings entryFangzhi Zuo
1. Catch invalid link_rate and link_count settings 2. Call dc interface to overwrite preferred link settings, and wait until next stream update to apply the new settings. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Log DMCUB trace buffer eventsLeo (Hanghong) Ma
[Why] We want to log DMCUB trace buffer events as Linux kernel traces. [How] Register an IRQ handler for DMCUB outbox0 interrupt in amdgpu_dm, and log the messages in the DMCUB tracebuffer to a new DMCUB TRACE_EVENT as soon as we receive the outbox0 IRQ from DMCUB FW. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: revert max lb lines changeDmytro Laktyushkin
Some hardware revisions do have a max number of lines limitation not honouring which can cause pstate switch underflow. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Add kernel doc to crc_rd_wrk fieldWayne Lin
[Why] Receive warning message below: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:380: warning: Function parameter or member 'crc_rd_wrk' not described in 'amdgpu_display_manager' [How] Add documentation for crc_rd_wrk. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: hide VGH asic specific structsDmytro Laktyushkin
The pmfw structs are specific to the asic and should not be present in base clk_mgr struct v2: squash in SI fix (Alex) Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display: Populate socclk entries for dcn2.1Roman Li
[Why] Dcn2.1 socclk entries in bandwidth params are not initialized. They are not used now, but will be needed for dml validation. [How] Populate socclk bw params from dpm clock table Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.xAlex Deucher
Commit 098214999c8f added fetching of the AUX_DPHY register values from the vbios, but it also changed the default values in the case when there are no values in the vbios. This causes problems with displays with high refresh rates. To fix this, switch back to the original default value for AUX_DPHY_TX_CONTROL. Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Igor Kravchenko <Igor.Kravchenko@amd.com> Cc: Aric Cyr <Aric.Cyr@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
2021-04-09drm/amd/display: use GFP_ATOMIC in dcn20_resource_constructNirmoy Das
Replace GFP_KERNEL with GFP_ATOMIC as dcn20_resource_construct() can't sleep. Partially fixes: https://bugzilla.kernel.org/show_bug.cgi?id=212311 as dcn20_resource_construct() also calls into SMU functions which does mutex_lock(). Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display/dc/calcs/dce_calcs: Remove some large variables from the stackLee Jones
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function ‘bw_calcs_init’: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2726:1: warning: the frame size of 1336 bytes is larger than 1024 bytes [-Wframe-larger-than=] v2: squash in sizeof fix Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack ↵Lee Jones
to the heap Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function ‘calculate_bandwidth’: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Colin Ian King <colin.king@canonical.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amd/display/dc/dce80/dce80_resource: Make local functions staticLee Jones
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: warning: no previous prototype for ‘dce80_aux_engine_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: warning: no previous prototype for ‘dce80_link_encoder_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: warning: no previous prototype for ‘dce80_clock_source_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: warning: no previous prototype for ‘dce80_clock_source_destroy’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: warning: no previous prototype for ‘dce80_validate_bandwidth’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: warning: no previous prototype for ‘dce80_validate_global’ [-Wmissing-prototypes] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Anthony Koo <Anthony.Koo@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu/display/dm: add missing parameter documentationAlex Deucher
Added a new parameter and forgot to update the documentation. Fixes: b6f91fc183f7 ("drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT interrupt work") Reviewed-by: Xiaogang Chen <xiaogang.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Xiaogang Chen <xiaogang.chen@amd.com>
2021-03-26Merge tag 'amd-drm-next-5.13-2021-03-23' of ↵Daniel Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.13-2021-03-23: amdgpu: - Debugfs cleanup - Various cleanups and spelling fixes - Flexible array cleanups - Initial AMD Freesync HDMI - Display fixes - 10bpc dithering improvements - Display ASSR support - Clean up and unify powerplay and swsmu interfaces - Vangogh fixes - Add SMU gfx busy queues for RV/PCO - PCIE DPM fixes - S0ix fixes - GPU metrics data fixes - DCN secure display support - Backlight type override - Add initial support for Aldebaran - RAS fixes - Prime fixes for A+A systems - Reset fixes - Initial resource cursor support - Drop legacy IO BAR requirements - Various power fixes amdkfd: - MMU notifier fixes - APU fixes radeon: - Debugfs cleanups - Flexible array cleanups UAPI: - amdgpu: Add a new INFO ioctl interface to query video capabilities rather than hardcoding them in userspace. This allows us to provide fine grained asic capabilities (e.g., if a particular part is bandwidth limited, we can limit the capabilities). Proposed userspace: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps - amdkfd: bump the driver version. There was a problem with reporting some RAS features on older versions of the driver. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21 Danvet: A bunch of conflicts all over, but it seems to compile ... I did put the call to dc_allow_idle_optimizations() on a single line since it looked a bit too jarring to be left alone. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com
2021-03-23drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbpsAlex Deucher
Move the function protoype to the right header and guard the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available with DCN. Fixes: 8c2f14c36f47ce ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Dillon Varone <dillon.varone@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
2021-03-23drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c:220:65-70: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:721:65-70: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:1139:67-72: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: Support vertical interrupt 0 for all dcn ASICWayne Lin
[Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: Fix vertical interrupt 0 registering issueWayne Lin
[Why] Find out that when we are registering vertical interrupt0, we get DC_IRQ_SOURCE_INVALID when call dc_interrupt_to_irq_source for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL. After analyzing, it's due to the defined value for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL is not (DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL + 1). It's not incremental sequence. [How] Use an array to record all vertical interrupt0 SRCID. While registering interrupt, use an incremental index to visit the array to get the right SRCID to register. Also add error handling to avoid potential pointer problem. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu/display: re-enable freesync video patchesNikola Cornij
Since this is a "revert of a revert", the end effect is that freesync video is back to its original state, the way it was before the first revert. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: Fix potential memory leakQingqing Zhuo
[Why] vblank_workqueue is never released. [How] Free it upon dm finish. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: add a func to disable accelerated modeYao Wang1
[Why] When driver disabled, we driver force the YCbCr420 to RGB, which means some register will be changed, such as RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0 When driver re-enabled, OS will Set Mode YCbCr420 again, which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV should to be 1 again, but dmub fw can’t update the register to 1 due to the mpll is not off [How] Adds an interface to disable accelerated mode bit, which allows DM to decide to call during driver disable/unload scenarios. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Yao Wang1 <Yao.Wang1@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: fix dcn3+ bw validation soc param update sequenceDmytro Laktyushkin
SOC needs to be updated to the WM set A values before validation happens. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: fix dml prefetch validationDmytro Laktyushkin
Incorrect variable used, missing initialization during validation. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: 3.2.127Aric Cyr
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add debug out when viewport too small * use max lb for latency hiding * System black screen hangs on driver load * Fix UBSAN warning for not a valid value for type '_Bool' * Fix for outbox1 ring buffer typecasting issue * Bypass sink detect when there are no eDPs connected * Increase precision for bpp in DSC calculations * Add changes for dsc bpp in 16ths and unify bw calculations * Correct algorithm for reversed gamma * Remove MPC gamut remap logic for DCN30 * Fix typo for helpers function name * Fix secure display lock problems * Fix no previous prototype warning * Separate caps for maximum RGB and YUV plane counts * Add debugfs to control DMUB trace buffer events * [FW Promotion] Release 0.0.56 * DCHUB underflow counter increasing in some scenarios * fix dml prefetch validation * fix dcn3+ bw validation soc param update sequence * add a func to disable accelerated mode * Fix potential memory leak Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: DCHUB underflow counter increasing in some scenariosAric Cyr
[Why] When unplugging a display, the underflow counter can be seen to increase because PSTATE switch is allowed even when some planes are not blanked. [How] Check that all planes are not active instead of all streams before allowing PSTATE change. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: [FW Promotion] Release 0.0.56Anthony Koo
More updates to the comments to better describe the function of different cmds and parameters in the dmub interface. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/display: Add debugfs to control DMUB trace buffer eventsLeo (Hanghong) Ma
[Why] We want to have a debugfs interface to enable or disable DMCUB trace buffer events. [How] Add debugfs interface to enable or disable trace buffer events. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-03-31 03:59:36 +0000