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path: root/drivers/gpu/drm/amd/pm
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2022-03-31drm/amdgpu: Fix unique_id references for Sienna CichlidKent Russell
Since unique_id is only supported in PMFW 0x3A5300 and higher, we will only be able to use it inside Smu_Metrics_V3_t, which requires PMFW 0x3A4900 and higher. Remove the unique_id/serial_number references from the v1 and v2 tables to avoid any confusion, and return 0 if metrics_v1 or metrics_v2 are used to try to get the unique_id/serial_number. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-31drm/amdgpu: Add unique_id support for sienna cichlidKent Russell
This is being added to SMU Metrics, so add the required tie-ins in the kernel. Also create the corresponding unique_id sysfs file. v2: Add FW version check, remove SMU mutex v3: Fix style warning v4: Add MP1 IP_VERSION check to FW version check Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-31drm/amdgpu: Use metrics data function to get unique_id for AldebaranKent Russell
This is abstracted well enough in the get_metrics_data function, so use the function Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-31drm/amdgpu: Add UNIQUE_ID to MetricsMember_tKent Russell
This will allow us to use the generic *_get_metrics_data functions for ASICs that support unique_id Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-31drm/amdgpu: Use switch case for unique_idKent Russell
To ease readability, use switch to set unique_id as supported for the supported IP_VERSIONs, and set it to unsupported by default for all other ASICs. This makes it easier to add IP_VERSIONs later on, and makes it obvious that it is not supported by default, instead of the current logic that assumes that it is supported unless it is not one of the specified IP_VERSIONs. v2: Rebase onto previous IP_VERSION change Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <KevinYang.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-28drm/amd/pm: Check feature support using IP versionLijo Lazar
Instead of ASIC type, use GC and MP1 IP versions for feature support checks. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-28amdgpu/pm: Implement emit_clk_levels for vega10Darren Powell
(v1) - implement emit_clk_levels for vega10, based on print_clk_levels, but using sysfs_emit rather than sprintf - modify local int vars to use uint32_t to match arg type of called functions - add return of error codes - refactor OD_XXX cases to return early with -EOPNOTSUPP if !(hwmgr->od_enabled) Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-28amdgpu/pm: Add new hwmgr API function "emit_clock_levels"Darren Powell
Extend commit 7f36948c92b2 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset") Add new hwmgr API function "emit_clock_levels" - add member emit_clock_levels to pp_hwmgr_func - Implemented pp_dpm_emit_clock_levels - add pp_dpm_emit_clock_levels to pp_dpm_funcs Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-25drm/amdgpu/pm: add asic smu support checkStanley.Yang
It must check asic whether support smu before call smu powerplay function, otherwise it may cause null point on no support smu asic. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-25drm/amdgpu/pm: fix the Stable pstate Test in amdgpu_testYifan Zhang
If GFX DPM is disbaled, Stable pstate Test in amdgpu_test fails. Check GFX DPM statue before change clock level Log: [ 46.595274] [drm] Initialized amdgpu 3.46.0 20150101 for 0000:02:00.0 on minor 0 [ 46.599929] fbcon: amdgpudrmfb (fb0) is primary device [ 46.785753] Console: switching to colour frame buffer device 240x67 [ 46.811765] amdgpu 0000:02:00.0: [drm] fb0: amdgpudrmfb frame buffer device [ 131.398407] amdgpu 0000:02:00.0: amdgpu: Failed to set performance level! Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/pm: fix indenting in __smu_cmn_reg_print_error()Dan Carpenter
Smatch complains that the dev_err_ratelimited() is indented one tab more than the surrounding lines. drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:174 __smu_cmn_reg_print_error() warn: inconsistent indenting It looks like it's not a bug, just that the indenting needs to be cleaned up. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/pm: fix typos in commentsJulia Lawall
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/pm: use pm mutex to protect ecc info tableStanley.Yang
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/pm: Send message when resp status is 0xFCLijo Lazar
When PMFW is really busy, it will respond with 0xFC. However, it doesn't change the response register state when it becomes free. Driver should retry and proceed to send message if the response status is 0xFC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/pm: add send bad channel info functionStanley.Yang
support message SMU update bad channel info to update HBM bad channel info in OOB table Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amdgpu: change registers in error checking for smu 13.0.5Yifan Zhang
smu 13.0.5 use new registers for smu msg and param. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amd/pm: new v3 SmuMetrics data structure for Sienna CichlidDanijel Slivka
structure changed in smc_fw_version >= 0x3A4900, "uint16_t VcnActivityPercentage" replaced with "uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1" Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: enable gfxoff routine for GC 10.3.7Prike Liang
Enable gfxoff routine for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02gpu/amd: vega10_hwmgr: fix inappropriate private variable nameMeng Tang
In file vega10_hwmgr.c, the names of struct vega10_power_state * and struct pp_power_state * are confusingly used, which may lead to some confusion. Status quo is that variables of type struct vega10_power_state * are named "vega10_ps", "ps", "vega10_power_state". A more appropriate usage is that struct are named "ps" is used for variabled of type struct pp_power_state *. So rename struct vega10_power_state * which are named "ps" and "vega10_power_state" to "vega10_ps", I also renamed "psa" to "vega10_psa" and "psb" to "vega10_psb" to make it more clearly. The rows longer than 100 columns are involved. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Meng Tang <tangmeng@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-25drm/amdgpu: add gfxoff support for smu 13.0.5Yifan Zhang
this patch adds gfxoff support for smu 13.0.5 Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-25drm/amd/pm: refine smu 13.0.5 pp table codeYifan Zhang
Based on smu 13.0.5 features, refine pp table code. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-24drm/amd/pm: fix mode2 reset fail for smu 13.0.5Yifan Zhang
SMU MSG index should be used as parameter. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-24amdgpu/pm: Disable managing hwmon sysfs attributes for ONEVF modeDanijel Slivka
This patch prohibits performing of set commands on all hwmon attributes through sysfs in ONEVF mode. Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Acked-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-23drm/amd/pm: Fix missing prototype warningLijo Lazar
Fix below warning warning: no previous prototype for '__smu_get_enabled_features' [-Wmissing-prototypes] Fixes: f141e251474d67 ("drm/amd/pm: validate SMU feature enable message for getting feature enabled mask") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-22drm/amd/pm: validate SMU feature enable message for getting feature enabled maskPrike Liang
There's always miss the SMU feature enabled checked in the NPI phase, so let validate the SMU feature enable message directly rather than add more and more MP1 version check. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-18drm/amd/pm: add smu_v13_0_5_ppt implementationYifan Zhang
this patch adds smu_v13_0_5_ppt implementation. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-18drm/amd/pm: update smc message sequence for smu 13.0.5Yifan Zhang
this patch updates smc message sequence for smu 13.0.5. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-18drm/admgpu/pm: add smu 13.0.5 driver interface headersYifan Zhang
This patch is to add smu 13.0.5 driver interface headers. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/smu11.5: restore cclks in vangogh_set_performance_levelAlex Deucher
When we disable manual clock setting, we need to restore the cclks as well as the gfxclk. Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd: Refactor `amdgpu_aspm` to be evaluated per deviceMario Limonciello
Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: Add support for MP1 13.0.8Prike Liang
Set smu sw function and enable swSMU support for MP1. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd: smu7: downgrade voltage error to infoMario Limonciello
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: fix some OEM SKU specific stability issuesEvan Quan
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU specific stability issues. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: fulfill Sienna_Cichlid implementations for DriverSmuConfig settingEvan Quan
Fulfill the implementations for DriverSmuConfig setting on Sienna_Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: fulfill Navi1x implementations for DriverSmuConfig settingEvan Quan
Fulfill the implementations for DriverSmuConfig setting on Navi1x. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: enable pm sysfs write for one VF modeYiqing Yao
[why] pm sysfs should be writable in one VF mode as is in passthrough [how] do not remove write access on pm sysfs if device is in one VF mode Fixes: 11c9cc95f818 ("amdgpu/pm: Make sysfs pm attributes as read-only for VFs") Signed-off-by: Yiqing Yao <yiqing.yao@amd.com> Reviewed-by: Monk Liu <Monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-16drm/amd/pm: correct the default DriverSmuConfig table settingsEvan Quan
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the socket power alpha filter set as 10/100ms, we can correct that issue. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-14drm/amd/pm: correct the sequence of sending gpu reset msgYifan Zhang
the 2nd parameter should be smu msg type rather than asic msg index. Fixes: 7d38d9dc4ecc ("drm/amdgpu: add mode2 reset support for yellow carp") Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11drm/amd/pm: fulfill the support for DriverSmuConfig tableEvan Quan
Enable the support for DriverSmuConfig table on Navi1x and Sienna_Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige GobyEvan Quan
Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige Goby. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11amdgpu/pm: Add emit_clock_levels callsDarren Powell
(v4) Modifications to satisfy checkpatch --strict (v3) Rewrote patchset to order patches as (API, hw impl, usecase) - modified amdgpu_get_pp_od_clk_voltage to try amdgpu_dpm_emit_clock_levels and fallback to amdgpu_dpm_print_clock_levels if emit is not implemented. - modified amdgpu_get_pp_dpm_clock to try amdgpu_dpm_emit_clock_levels and fallback to amdgpu_dpm_print_clock_levels if emit is not implemented. - Newline is printed to buf if no output produced == Test == LOGFILE=pp_clk.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_od_clk_voltage pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_vclk pp_dpm_dclk " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11amdgpu/pm: Implement emit_clk_levels for navi10Darren Powell
(v4) Modifications to satisfy checkpatch --strict (v3) Rewrote patchset to order patches as (API, hw impl, usecase) - implement emit_clk_levels for navi10, based on print_clk_levels, but using sysfs_emit without smu_cmn_get_sysfs() workaround Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11drm/amd/pm: fix enabled features retrieving on Renoir and Cyan SkillfishEvan Quan
For Cyan Skillfish and Renoir, there is no interface provided by PMFW to retrieve the enabled features. So, we assume all features are enabled. Fixes: 7ade3ca9cdb5 ("drm/amd/pm: correct the usage for 'supported' member of smu_feature structure") Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-09drm/amd/pm: correct hwmon power label nameYang Wang
only vangogh has 2 types of hwmon power node: "fastPPT" and "slowPPT", the other asic only has 1 type of hwmon power node: "PPT". Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-09drm/amd/pm: fix hwmon node of power1_label create issueYang Wang
it will cause hwmon node of power1_label is not created. v2: the hwmon node of "power1_label" is always needed for all ASICs. and the patch will remove ASIC type check for "power1_label". Fixes: ae07970a0621d6 ("drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangogh") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-09drm/amd/pm: drm/amd/pm: disable GetPptLimit message in sriov modeYang Wang
PPT limit cannot be queried from VF Fixes: f3527a6483fbcc ("drm/amd/pm: Enable sysfs required by rocm-smi tool for One VF mode") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-07drm/amd/pm: add missing prototypes to amdgpu_dpm_internalMaíra Canal
Include the header with the prototype to silence the following clang warnings: drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:29:6: warning: no previous prototype for function 'amdgpu_dpm_get_active_displays' [-Wmissing-prototypes] void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:29:1: note: declare 'static' if the function is not intended to be used outside of this translation unit void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) ^ static drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:76:5: warning: no previous prototype for function 'amdgpu_dpm_get_vrefresh' [-Wmissing-prototypes] u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.c:76:1: note: declare 'static' if the function is not intended to be used outside of this translation unit u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) ^ static 2 warnings generated. Besides that, remove the duplicated prototype of the function amdgpu_dpm_get_vblank_time in order to keep the consistency of the headers. Fixes: 6ddbd37f1074 ("drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Maíra Canal <maira.canal@usp.br> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-07drm/amd/pm: fix error handlingTom Rix
clang static analysis reports this error amdgpu_smu.c:2289:9: warning: Called function pointer is null (null dereference) return smu->ppt_funcs->emit_clk_levels( ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ There is a logic error in the earlier check of emit_clk_levels. The error value is set to the ret variable but ret is never used. Return directly and remove the unneeded ret variable. Fixes: 5d64f9bbb628 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-07drm/amd/pm: revise the implementation of ↵Evan Quan
smu_cmn_disable_all_features_with_exception As there is no internal cache for enabled ppfeatures now. Thus the 2nd parameter will be not needed any more. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-07drm/amd/pm: avoid consecutive retrieving for enabled ppfeaturesEvan Quan
As the enabled ppfeatures are just retrieved ahead. We can use that directly instead of retrieving again and again. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-04-28 23:47:51 +0000