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path: root/drivers/gpu/drm/exynos/regs-mixer.h
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2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-12-05drm/exynos: mixer: Fix color range settingChristoph Manszewski
Color format and color range was set based on resolution. Change that, by splitting range and format. Leave color format setting as it is, set color range based on drm_display_mode using drm_default_quant_range helper function. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20181128 using modetest. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-10-01drm/exynos: mixer: Make plane alpha configurableChristoph Manszewski
The mixer hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-05-04drm/exynos/mixer: fix synchronization check in interlaced modeAndrzej Hajda
In case of interlace mode video processor registers and mixer config register must be check to ensure internal state is in sync with shadow registers. This patch fixes page-faults in interlaced mode. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2017-06-01drm/exynos: mixer: document YCbCr magic numbersTobias Jakobi
The output stage of the mixer uses YCbCr for the internal computations, which is the reason that some registers take YCbCr related data as input. In particular this applies to MXR_BG_COLOR{0,1,2} and MXR_CM_COEFF_{Y,CB,CR}. Document the formatting of the data which we write to these registers. While at it, unify wording of comments in the register header. Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-01-13drm/exynos: mixer: refactor layer setupMarek Szyprowski
Properly configure blending properties of given hardware layer based on the selected pixel format. Currently only per-pixel-based alpha is possible when respective pixel format has been selected. Configuration of global, per-plane alpha value, color key and background color will be added later. This patch is heavily inspired by earlier work done by Tobias Jakobi <tjakobi@math.uni-bielefeld.de>. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-01-13drm/exynos: mixer: set window priority based on zposMarek Szyprowski
'zpos' plane property is configurable, so adjust hardware layers priority based on the zpos value. 'zpos' value shifted by one can be used directly as hw priority value and stored to the registers, because mixer accepts priority values from 1 to 15 (0 means that layer is disabled). This patch also changes the default layer priority to match already exposed initial zpos values. The initial configuration is now: [top] video > gfx layer1 > gfx layer0 [bottom]. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-04-13drm/exynos: fix typos in hdmi and mixerTobias Jakobi
Use the correct spelling for 'progressive'. Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2014-06-24drm/exynos: stop mixer before gating clocks during poweroffRahul Sharma
Mixer should be power gated only after it is gracefully stopped. The recommended sequence is to Stop the mixer and wait till it enters to IDLE state before gating the clocks and power to the mixer. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-06-28drm/exynos: add support for exynos5420 mixerRahul Sharma
Add support for exynos5420 mixer IP in the drm mixer driver. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2012-10-05drm: exynos: hdmi: add support for exynos5 mixerRahul Sharma
This patch adds support for exynos5 mixer with device tree enabled. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Fahad Kunnathadi <fahad.k@samsung.com> Signed-off-by: Kyungmin.park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2011-12-29drm/exynos: added hdmi display supportSeung-Woo Kim
This patch is hdmi display support for exynos drm driver. There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv and some low level code is already in s5p-tv and even headers for register define are almost same. but in this patch, we decide not to consider separated common code with s5p-tv. Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc. 1. mixer. The piece of hardware responsible for mixing and blending multiple data inputs before passing it to an output device. The mixer is capable of handling up to three image layers. One is the output of VP. Other two are images in RGB format. The blending factor, and layers' priority are controlled by mixer's registers. The output is passed to HDMI. 2. vp (video processor). It is used for processing of NV12/NV21 data. An image stored in RAM is accessed by DMA. The output in YCbCr444 format is send to mixer. 3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes pixel data from mixer and transforms it into data frames. The output is send to HDMIPHY interface. 4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to HDMI connector. Basically, it contains a PLL that produces source clock for mixer, vp and hdmi. 5. ddc (display data channel). It is dedicated i2c channel to exchange display information as edid with display monitor. With plane support, exynos hdmi driver fully supports two mixer layes and vp layer. Also vp layer supports multi buffer plane pixel formats having non contigus memory spaces. In exynos drm driver, common drm_hdmi driver to interface with drm framework has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls them. mixer controls all overlay layers in both mixer and vp. Vblank interrupts for hdmi are handled by mixer internally because drm framework cannot support multiple irq id. And pipe number is used to check which display device irq happens. History v2: this version - drm plane feature support to handle overlay layers. - multi buffer plane pixel format support for vp layer. - vp layer support RFCv1: original - at https://lkml.org/lkml/2011/11/4/164 Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>