summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_bw.h
AgeCommit message (Expand)Author
2023-06-07drm/i915/mtl: find the best QGV point for the SAGV configurationVinod Govindapillai
2023-01-25drm/i915/display: add intel_display_limits.h for key enumsJani Nikula
2022-03-21drm/i915: Add "maximum pipe read bandwidth" checksVille Syrjälä
2022-03-21drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä
2022-03-21drm/i915: Nuke intel_bw_calc_min_cdclk()Ville Syrjälä
2022-02-16drm/i915: Widen the QGV point maskVille Syrjälä
2020-05-22drm/i915: Fix includes and local vars orderStanislav Lisovskiy
2020-05-21drm/i915: Adjust CDCLK accordingly to our DBuf bw needsStanislav Lisovskiy
2020-05-14drm/i915: Restrict qgv points which don't have enough bandwidth.Stanislav Lisovskiy
2020-05-04drm/i915: Track active_pipes in bw_stateStanislav Lisovskiy
2020-05-04drm/i915: Use bw state for per crtc SAGV evaluationStanislav Lisovskiy
2020-04-17drm/i915: Add intel_atomic_get_bw_*_state helpersStanislav Lisovskiy
2020-01-31drm/i915: Convert bandwidth state to global stateVille Syrjälä
2019-12-24drm/i915/display: cleanup intel_bw_state on i915 module removalPankaj Bharadiya
2019-08-07drm/i915/bw: make intel_atomic_get_bw_state() staticJani Nikula
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula
generated by cgit (git 2.34.1) at 2025-03-23 10:17:41 +0000