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path: root/drivers/gpu/drm/i915/display/intel_psr.c
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2023-10-26drm/i915/display: Move psr related module parameters under displayJouni Högander
Move psr related module parameters under display. Also fix error in enable_psr2_sel_fetch module parameter descrtiption. It was saying disabled by default while it's vice versa. Also psr_safest_params was missing default value in description. This is now added. v2: - Fix enable_psr2_sel_fetch description. - Add default value into psr_safest_params description. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231024124109.384973-5-jouni.hogander@intel.com
2023-10-13drm/i915/lnl: Remove watchdog timers for PSRMika Kahola
Watchdog timers for Lunarlake HW were removed for PSR/PSR2 The patch removes the use of these timers from the driver code. BSpec: 69895 v2: Reword commit message (Ville) Drop HPD mask from LNL (Ville) Revise masking logic (Jouni) v3: Revise commit message (Ville) Revert HPD mask removal as irrelevant for this patch (Ville) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231010095233.590613-1-mika.kahola@intel.com
2023-10-06drm/i915/psr: Unify PSR pre/post plane update hooksVille Syrjälä
intel_psr_pre_plane_update() operates on a per-crtc level, whereas intel_psr_post_plane_update() operates on the whole atomic commit, for no real reason that I can see. Adjust intel_psr_post_plane_update() to match the intel_psr_pre_plane_update() approach. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-09-06drm/i915/psr: Add psr sink error status into sink status debugfsJouni Högander
Normally PSR errors detected by the panel are triggering HPD interrupt and seen as error in dmesg. Some panels are not triggering the interrupt even it is requested and they are detecting error. Due to this it would be good to have possibility to check panel detected errors. Add PSR error status into PSR sink status debugfs interface. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828083107.1520501-1-jouni.hogander@intel.com
2023-09-04drm/i915/psr: Clear frontbuffer busy bits on flipJouni Högander
We are planning to move flush performed from work queue. This means it is possible to have invalidate -> flip -> flush sequence. Handle this by clearing possible busy bits on flip. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230901093500.3463046-3-jouni.hogander@intel.com
2023-08-31drm/i915: add minimal i915_gem_object_frontbuffer.hJani Nikula
Split out frontbuffer related declarations and static inlines from gem/i915_gem_object.h into new gem/i915_gem_object_frontbuffer.h. The main goal is to reduce header interdependencies. With gem/i915_gem_object.h including display/intel_frontbuffer.h, modification of the latter causes a whopping 300+ objects to be rebuilt, while many of the source files actually needing it aren't explicitly including it at all. After the change, only 21 objects depend on display/intel_frontbuffer.h, directly or indirectly. Cc: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230830085127.2416842-1-jani.nikula@intel.com
2023-08-29drm/i915/psr: Apply Wa_14015648006 for all display 14 steppingsJouni Högander
According to recent Bspec Wa 14015648006 has to be applied for all display 14 steppings. Bspec: 66624 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230829094435.2100669-1-jouni.hogander@intel.com
2023-08-21drm/i915: Eliminate IS_MTL_DISPLAY_STEPMatt Roper
Stepping-specific display behavior shouldn't be tied to MTL as a platform, but rather specifically to the Xe_LPD+ IP. Future non-MTL platforms may re-use this IP and will need to follow the exact same logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the display IP version. v2: - Rename macro to IS_DISPLAY_IP_STEP for consistency with the corresponding GT macro and handle steppings the same way. v3: - Drop the automatic "STEP_" pasting. v4: - Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE / IS_DISPLAY_STEP building blocks and make the parameters from/until instead of begin/fixed. (Jani) - Fix usage details in comment. v5: - Tweak macro comment. (Gustavo) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-17-matthew.d.roper@intel.com
2023-08-07drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane
Driver refers to the platform Alderlake P as ADLP in places and ALDERLAKE_P in some. Making the consistent change to avoid confusion of the right naming convention for the platform. v2: - Unrolled wrapper IS_ADLP_GRAPHICS_STEP and Replace - Added IS_ALDERLAKE_P() && IS_GRAPHICS_STEP() (Jani/Tvrtko). v3: - Removed unused macros of display steps. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-11-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace JSL with JASPERLAKE. Unroll IS_JSL_EHL() define with IS_JASPERLAKE() || IS_ELKHARTLAKE() condition. Change in the display step define for Jasperlake. v2: - Change subject prefix skl instead of SKL(Anusha) v3: - Remove the use of define IS_JSL_EHL. - Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE() - Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP (Jani/Tvrtko) v4: - Removed unused macro v5: - Resolved valid checkpatch warning(Jani) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-9-dnyaneshwar.bhadane@intel.com
2023-06-21drm/i915/psr: Use hw.adjusted mode when calculating io/fast wake timesJouni Högander
Encoder compute config is changing hw.adjusted mode. Uapi.adjusted mode doesn't get updated before psr compute config gets called. This causes io and fast wake line calculation using adjusted mode containing values before encoder adjustments. Fix this by using hw.adjusted mode instead of uapi.adjusted mode. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8475 Fixes: cb42e8ede5b4 ("drm/i915/psr: Use calculated io and fast wake lines") Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230620111745.2870706-1-jouni.hogander@intel.com
2023-06-16drm/i915/psr: Allow PSR with sprite enabled on hsw/bdwVille Syrjälä
Can't see why we'd want the sprite blocking PSR entry. Mask it out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-13-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdwVille Syrjälä
WA 0479 says: "Do not skip both TP1 and TP2/TP3". Let's just stick the minimum 100us TP2/3 time in there to avoid that. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-12-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: Do no mask display register writes on hsw/bdwVille Syrjälä
hsw/bdw lack the pipe register vs. display register distinction in their PSR masking capabilities. So to keep our CURSURFLIVE tricks working we need to just unmask all display register writes on these platforms. The downside being that any display regitster (eg. even SWF regs) will cause a PSR exit. Note that WaMaskMMIOWriteForPSR asks us to mask this on bdw, but that won't work since we need those CURSURFLIVE tricks. Observations on actual hardware show that this causes one extra PSR exit ~every 10 seconds, which is pretty much irrelevant. I suspect this is due to the pcode poking at IPS_CTL. Disabling IPS does not stop it however, so either I'm wrong or pcode pokes at the register regardless of whether it's actually trying to enable/disable IPS. Also when the machine is busy (eg. just running 'find /') these extra PSR exits cease, which again points at pcode or some other PM entity as being the culprit. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-11-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: HSW/BDW have no PSR2Ville Syrjälä
Deal with HSW/BDW in transcoder_has_psr2(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-7-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setupVille Syrjälä
Reintroduce the special PSR AUX CH setup for hsw/bdw. Not all of it was even removed (BDW AUX data registers were left behind). Update the code to use REG_BIT() & co. while at it. v2: Define the SRD_AUX_CTL bits in terms of DP_AUX_CTL bits (Jouni) Add a comment explaining the hand rolled DPCD write (Jouni) Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-6-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: Reintroduce HSW PSR1 registersVille Syrjälä
Add back hsw'w special SRD/PSR1 registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-5-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-16drm/i915/psr: Wrap PSR1 register with functionsVille Syrjälä
In preparation for re-introducing HSW's different PSR1 register offeets let's just wrap all the registers into functions. Avoids having to make the register macros more complex. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-4-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-06-10drm/i915: add a dedicated workqueue inside drm_i915_privateLuca Coelho
In order to avoid flush_scheduled_work() usage, add a dedicated workqueue in the drm_i915_private structure. In this way, we don't need to use the system queue anymore. This change is mostly mechanical and based on Tetsuo's original patch[1]. v6 by Jani: - Also create unordered_wq for mock device Link: https://patchwork.freedesktop.org/series/114608/ [1] Cc: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c816ebe17ef08d363981942a096a586a7658a65e.1686231190.git.jani.nikula@intel.com
2023-04-20drm/i915/psr: Sprinkle cpu_transcoder variables aroundVille Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local cpu_transcoder variables. Ideally I'd like the whole PSR code to stop using intel_dp except during a full modeset, but dunno yet if that's possible. But the less 'intel_dp' we have sprad around the easier that should be to figure out eventually. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-9-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-04-20drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all platformsVille Syrjälä
The fact that DC states reset the PSR perofrmance counter is no reason not to include it in the debug output. But let's keep the comment there to remind people about that caveat. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-8-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-04-20drm/i915/psr: Define more PSR mask bitsVille Syrjälä
Define more of the PSR mask bits, and describe in detail what some of them do. Even if we don't set them all from the driver they can be very useful during PSR debugging. Having to trawl through bspec every time to find them is not fun, and re-reverse engineering the behaviour every time is time consuming (even if a bit more fun than spec trawling). v2: Moar bits Put the description into a comment to be easily available v2: Fix the BDW_UNMASK_VBL_TO_REGS_IN_SRD/HSW_UNMASK_VBL_TO_REGS_IN_SRD description Rebase due to intel_psr_regs.h Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-6-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-04-20drm/i915/psr: Use intel_de_rmw()Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-5-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-04-20drm/i915/psr: Clean up PSR register defininitionsVille Syrjälä
Use REG_BIT() & co. to make the PSR register definitions nicer. v2: Rebase due to intel_psr_regs.h Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-4-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-04-13drm/i915: Flag purely internal commits to not clear crtc_state->inheritedVille Syrjälä
If we have to force the hardware to go through a full modeset due to eg. cdclk reprogramming, we need to preserve crtc_state->inherited for all crtcs that have not otherwise gone through the whole compute_config() stuff after connectors have been detected. Otherwise eg. cdclk induced modeset glk_force_audio_cdclk() will clear the inherited flag, and thus the first real commit coming from userspace later on will not be forced through the full .compute_config() path and so eg. audio state may not get properly recomputed. But instead of adding all kinds of ad-hoc crtc_state->inherited preservation hacks all over, let's change things so that we only clear it for the crtcs directly included in userspace/client initiated commits. Should be far less fragile since now we just need to remember to flag the internal commits, and not worry about where new crtcs might get pulled in. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5260 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328122357.1697-1-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
2023-04-04drm/i915/psr: split out PSR regs to a separate fileJani Nikula
Clean up i915_reg.h by splitting out PSR regs to display/intel_psr_regs.h. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230331090949.2858951-2-jani.nikula@intel.com
2023-03-31drm/i915/psr: Implement Display WA #1136Jouni Högander
Implement Display WA #1136 for Pre-ICL. Bspec: 21664 v2: Handle disable psr in pre/post plane hooks Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-7-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Check that vblank is long enough for psr2Jouni Högander
Ensure vblank >= psr2 vblank where Psr2 vblank = PSR2_CTL Block Count Number maximum line count. Bspec: 71580, 49274 v2: Use calculated block count number maximum line count Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-6-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Add helpers for block count number handlingJouni Högander
Add helpers to make it more clear how PSR2_CTL[Block Count Number] is configured. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-5-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Implement Wa_14015648006Jouni Högander
PSR WM optimization should be disabled based on any wm level being disabled. Also same WA should be applied for ICL as well. Bspec: 71580 v5: - Set in pre plane hook and clear in post plane hook v4: - Handle mode change in psr enable/disable - Handle wm_level_disable changes separately in pre plane hook v3: - Split patch v2: - set/clear chicken bit in post_plane_update - apply for ICL as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-4-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006Jouni Högander
Wa_16013835468 is a separate from Wa_14015648006 and needs to be applied for display version 12. Fix this by removing all the references to Wa_14015648006 and apply Wa_16013835468 according to Bspec. Also move workaround into separate function as a preparation for Wa_14015648006 implementation. Bspec: 55378 v3: - apply for display version 12 only v2: - keep applying the wa in intel_psr_enable_source Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-3-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Unify pre/post hooksJouni Högander
pre/post hooks are doing things differently. Unify them. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-2-jouni.hogander@intel.com
2023-03-20drm/i915/psr: clean up PSR debugfs sink status error handlingJani Nikula
Handle errors first and return early, and reduce indentation on the happy day code path. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-3-jani.nikula@intel.com
2023-03-20drm/i915/psr: switch PSR debugfs to struct intel_connectorJani Nikula
Prefer struct intel_connector over struct drm_connector. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-2-jani.nikula@intel.com
2023-03-20drm/i915/psr: move PSR debugfs to intel_psr.cJani Nikula
Move the debugfs next to the implementation. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-1-jani.nikula@intel.com
2023-03-06drm/i915/power: move dc state members to struct i915_power_domainsJani Nikula
There's only one reference to the struct intel_dmc members dc_state, target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the question why they are under struct intel_dmc to begin with. Moreover, the only references to i915->display.dmc outside of intel_dmc.c are to these members. They don't belong. Move them from struct intel_dmc to struct i915_power_domains, which seems like a more suitable place. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-1-jani.nikula@intel.com
2023-03-01drm/i915/psr: Fix the delayed vblank w/aVille Syrjälä
Fix the code to correctly determine whether delayed vblank is used or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230127173044.24108-3-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-02-24drm/i915/psr: Use calculated io and fast wake linesJouni Högander
Currently we are using hardcoded 7 for io and fast wake lines. According to Bspec io and fast wake times are both 42us for DISPLAY_VER >= 12 and 50us and 32us for older platforms. Calculate line counts for these and configure them into PSR2_CTL accordingly Use 45 us for the fast wake calculation as 42 seems to be too tight based on testing. Bspec: 49274, 4289 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Fixes: 64cf40a125ff ("drm/i915/psr: Program default IO buffer Wake and Fast Wake") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7725 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230221085304.3382297-1-jouni.hogander@intel.com
2023-02-20drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCYVille Syrjälä
The PSR code has no business mucking around with the vblank delay. Currently nothing that depends on knowing the exact vblank start scanline (eg. vblank evasion) is aware of this and so will not work correctly. The w/a seems to be for pre-production hw only, so let's just nuke it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-02-17drm/i915: Give CPU transcoder timing registers TRANS_ prefixVille Syrjälä
Name the CPU transcoder timing registers TRANS_FOO rather than just FOO. This is the modern name, after the pipe/transcoder split happened. Makes it a bit more obvious whether you pass in a pipe or a transcoder. PIPESRC is a bit special as it's a pipe register, even though it lives in the transcoder registers range (0x60000 instead of 0x70000). And BCLRPAT I suppose is a transcoder register (since it has something to do with the timing generator), but it doesn't even exist after gen4 so I left it to use the only name it ever had in bspec. And while at it let's pass in the correct enum in few more places why don't we. Although in all those places the distinction doesn't matter. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-02-16drm/i915/display/panel: use intel_de_rmw if possible in panel related codeAndrzej Hajda
The helper makes the code more compact and readable. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230105131046.2173431-7-andrzej.hajda@intel.com
2023-01-30drm/i915/tgl: Drop support for pre-production steppingsMatt Roper
Several post-TGL platforms have been brought up now, so we're well past the point where we usually drop the workarounds that are only applicable to internal/pre-production hardware. Production TGL hardware always has display stepping C0 or later and GT stepping B0 or later (this is true for both the original TGL and the U/Y subplatform). Bspec 44455 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230127224313.4042331-2-matthew.d.roper@intel.com
2023-01-30drm/i915/psr: Split sel fetch plane configuration into arm and noarmJouni Högander
SEL_FETCH_CTL registers are armed immediately when plane is disabled. SEL_FETCH_* instances of plane configuration are used when doing selective update and normal plane register instances for full updates. Currently all SEL_FETCH_* registers are written as a part of noarm plane configuration. If noarm and arm plane configuration are not happening within same vblank we may end up having plane as a part of selective update before it's PLANE_SURF register is written. Fix this by splitting plane selective fetch configuration into arm and noarm versions and call them accordingly. Write SEL_FETCH_CTL in arm version. v3: - add arm suffix into intel_psr2_disable_plane_sel_fetch v2: - drop color_plane parameter from arm part - dev_priv -> i915 in arm part Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230130080651.3796929-1-jouni.hogander@intel.com
2023-01-26drm/i915/psr: Implement Wa_14014971492Jouni Högander
Implement Wa_14014971492 and apply it for affected platforms. Bspec: 52890, 54369, 55378, 66624 v2: Adjust platforms where applied Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230124102636.2567292-2-jouni.hogander@intel.com
2023-01-17drm/i915/psr: Implement Wa_14015648006Jouni Högander
Add 4th pipe and extend TGL Wa_16013835468 to support ADLP, MTL and DG2 and all TGL steppings. BSpec: 54369, 55378, 66624 v3: - commit message modified v2: - apply for PSR1 as well - remove stepping information from comments Cc: Matt Roper <matthew.d.roper@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230105065637.2063311-1-jouni.hogander@intel.com
2023-01-16drm/i915/display: drop redundant display/ from #includesJani Nikula
Drop the redundant sub-directory from #includes under display/. Group and sort the results. v2: Rebase Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230104153258.453431-1-jani.nikula@intel.com
2022-12-23drm/i915/psr: Add continuous full frame bit together with singleJouni Högander
Currently we are observing occasionally display flickering or complete freeze. This is narrowed down to be caused by single full frame update (SFF). SFF bit after it's written gets cleared by HW in subsequent vblank i.e. when the update is sent to the panel. SFF bit is required to be written together with partial frame update (PFU) bit. After the SFF bit gets cleared by the HW psr2 man trk ctl register still contains PFU bit. If there is subsequent update for any reason we will end up having selective update/fetch configuration where start line is 0 and end line is 0. Also selective fetch configuration for the planes is not properly performed. This seems to be causing problems with some panels. Using CFF without SFF doesn't work either because it may happen that psr2 man track ctl register is overwritten by next update before vblank triggers sending the update. This is causing problems to psr_invalidate/flush. Using CFF and SFF together solves the problems as SFF is cleared only by HW in subsequent vblank and the update gets sent. Fix the flickering/freeze issue by keeping CFF bit as set when PSR2 is enabled unless there is a properly configured selective update via atomic commit. v2: - Improve commit message and comments - No functional changes This is also workaround for HSD 14014971508 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reported-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Tested-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221201072308.1905679-1-jouni.hogander@intel.com
2022-12-12drm/i915/mtl: Initial display workaroundsJouni Högander
This patch introduces initial workarounds for mtl platform v2: switch IS_MTL_DISPLAY_STEP to use IS_METEORLAKE from testing display ver. (Tvrtko) v3: clerical issues, extend 16015201720 to mtl. (MattR) v4: make sure 16015201720 includes display 13. (MattR) Bspec: 66624 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221209220543.502047-1-matthew.s.atwood@intel.com
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula
Turns out many of the files that need i915_reg.h get it implicitly via {display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h -> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h, makes sense to drop it, but that requires adding quite a few new includes all over the place. Prefer including i915_reg.h where needed instead of adding another implicit include, because eventually we'll want to split up i915_reg.h and only include the specific registers at each place. Also some places actually needed i915_irq.h too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e78a2e0ac1bffaf5af3b5ccc21dff05e6518cef.1668008071.git.jani.nikula@intel.com
2022-11-03drm/i915/psr: Remove inappropriate DSC slice alignment warningJouni Högander
Selective update area is now aligned with DSC slice height when DSC is enabled. Remove inappropriate warning about missing DSC alignment. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221102174544.2288205-3-jouni.hogander@intel.com
generated by cgit (git 2.34.1) at 2024-05-27 16:16:23 +0000