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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.c
AgeCommit message (Expand)Author
2022-02-21drm/i915/dg2: Print PHY name properly on calibration errorMatt Roper
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula
2021-11-03drm/i915: Query the vswing levels per-lane for snps phyVille Syrjälä
2021-10-14drm/i915: Remove pointless extra namespace from dkl/snps buf trans structsVille Syrjälä
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä
2021-09-30drm/i915: s/ddi_translations/trans/Ville Syrjälä
2021-08-30drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna
2021-08-26drm/i915/snps: constify struct intel_mpllb_state arrays harderJani Nikula
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper
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