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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2015-10-13drm/i915: Parametrize and fix SWF registersVille Syrjälä
2015-10-13drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä
2015-10-13drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä
2015-10-13drm/i915: Protect register macro argumentsVille Syrjälä
2015-10-13drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä
2015-10-13drm/i915: Eliminate weird parameter inversion from BXT PPS registersVille Syrjälä
2015-10-07drm/i915/bxt: Set time interval unit to 0.833usAkash Goel
2015-10-06drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelistJordan Justen
2015-10-02drm/i915/bxt: Modify BXT BLC according to VBT changesSunil Kamath
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma
2015-10-02drm/i915/bxt: DSI enable for BXTShashank Sharma
2015-10-02drm/i915: rename INSTDONE1 to GEN4_INSTDONE1Imre Deak
2015-10-02drm/i915: rename INSTDONE to GEN2_INSTDONEImre Deak
2015-10-02drm/i915: remove duplicate names for the render ring INSTDONE registerImre Deak
2015-10-01drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä
2015-09-30drm/i915/bdw: Check for slice, subslice and EU count for BDWŁukasz Daniluk
2015-09-30drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä
2015-09-30drm/i915: Renaming CCK related reg definitionsVandana Kannan
2015-09-30drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASEVille Syrjälä
2015-09-30drm/i915: Parametrize PALETTE and LGC_PALETTEVille Syrjälä
2015-09-30drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSRVille Syrjälä
2015-09-30drm/i915: Add LO/HI PRIVATE_PAT registersVille Syrjälä
2015-09-30drm/i915: Parametrize fence registersVille Syrjälä
2015-09-30drm/i915/bxt: Set oscaledcompmethod to enable scale valueSonika Jindal
2015-09-23drm/i915: Parametrize DDI_BUF_TRANS registersVille Syrjälä
2015-09-23drm/i915: Parametrize TV luma/chroma filter registersVille Syrjälä
2015-09-23drm/i915: Parametrize ILK turbo registersVille Syrjälä
2015-09-23drm/i915: Parametrize FBC_TAG registersVille Syrjälä
2015-09-23drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITSVille Syrjälä
2015-09-23drm/i915: Implement stolen reserved detection for ctg/elkVille Syrjälä
2015-09-23drm/i915/bxt: DSI prepare changes for BXTShashank Sharma
2015-09-23drm/i915/bxt: Enable BXT DSI PLLShashank Sharma
2015-09-14drm/i915/gen9: WA ST Unit Power Optimization DisableRobert Beckett
2015-09-14drm/i915/bxt: Add WaSetClckGatingDisableMediaArun Siluvery
2015-09-07drm/i915: initialize backlight max from VBTJani Nikula
2015-09-02drm/i915: Rewrite BXT HPD code to conform to pre-existing styleVille Syrjälä
2015-09-02drm/i915: Add port A HPD support for SPTVille Syrjälä
2015-09-02drm/i915: Rename BXT PORTA HPD definesVille Syrjälä
2015-09-02drm/i915: Clean up various HPD definesVille Syrjälä
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä
2015-08-26drm/i915/skl: enable DDI-E hotplugXiong Zhang
2015-08-26drm/i915: Change SRM, LRM instructions to use correct lengthArun Siluvery
2015-08-14drm/i915: Interrupt routing for GuC submissionDave Gordon
2015-08-14drm/i915: GuC-specific firmware loaderAlex Dai
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