summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2019-10-08drm/i915/tgl: Add DC3CO counter in i915_dmc_infoAnshuman Gupta
2019-10-08drm/i915/tgl: Add DC3CO required register and bitsAnshuman Gupta
2019-10-04drm/i915: Implement a better i945gm vblank irq vs. C-states workaroundVille Syrjälä
2019-10-04drm/i915: Fix audio power up sequence for gen10+ displayKai Vehmanen
2019-10-02drm/i915/mg: Use tc_port instead of port parameter to MG registersJosé Roberto de Souza
2019-09-27drm/i915/tgl: Add dkl phy programming sequencesClinton A Taylor
2019-09-27drm/i915/tc: Update DP_MODE programmingClinton A Taylor
2019-09-26drm/i915: Add definitions for MI_MATH commandMichał Winiarski
2019-09-25Revert "drm/i915/color: Extract icl_read_luts()"Swati Sharma
2019-09-24drm/i915: Add Pipe D cursor ctrl register for Gen12Ankit Nautiyal
2019-09-23drm/i915/tgl: Add dkl phy registersVandita Kulkarni
2019-09-23drm/i915/tgl: Finish modular FIA support on registersJosé Roberto de Souza
2019-09-23drm/i915: save AUD_FREQ_CNTRL state at audio domain suspendKai Vehmanen
2019-09-23drm/i915/dsb: function to trigger workload execution of DSB.Animesh Manna
2019-09-23drm/i915/dsb: functions to enable/disable DSB engine.Animesh Manna
2019-09-23drm/i915/dsb: Check DSB engine status.Animesh Manna
2019-09-23drm/i915/color: Extract icl_read_luts()Swati Sharma
2019-09-21drm/i915/tgl: s/ss/eu fuse reading supportDaniele Ceraolo Spurio
2019-09-20drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVBVille Syrjälä
2019-09-20drm/i915: Set up ILK/SNB csc unit properly for YCbCr outputVille Syrjälä
2019-09-20drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSWVille Syrjälä
2019-09-20drm/i915: Simplify intel_get_crtc_ycbcr_config()Ville Syrjälä
2019-09-20drm/i915: Fix HSW+ DP MSA YCbCr colorspace indicationVille Syrjälä
2019-09-20Revert "drm/i915/tgl: Implement Wa_1406941453"Chris Wilson
2019-09-19drm/i915/tgl: Implement Wa_1406941453Michel Thierry
2019-09-19drm/i915/tgl: Implement Wa_1409142259Radhakrishna Sripada
2019-09-10drm/i915/display: Extract chv_read_luts()Swati Sharma
2019-09-10drm/i915/display: Extract i965_read_luts()Swati Sharma
2019-09-04drm/i915/tgl: move DP_TP_* to transcoderLucas De Marchi
2019-09-04drm/i915/tgl: Access the right register when handling PSR interruptionsJosé Roberto de Souza
2019-09-04drm/i915/psr: Only handle interruptions of the transcoder in useJosé Roberto de Souza
2019-09-04drm/i915/display: Extract glk_read_luts()Swati Sharma
2019-09-04drm/i915/display: Extract ilk_read_luts()Swati Sharma
2019-09-04drm/i915/display: Extract i9xx_read_luts()Swati Sharma
2019-08-30drm/i915: Allow /2 CD2X divider on gen11+Matt Roper
2019-08-30drm/i915: parameterize SDE hotplug registersLucas De Marchi
2019-08-30drm/i915: parameterize south hpd macrosLucas De Marchi
2019-08-30drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+Ramalingam C
2019-08-23drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gatingMichel Thierry
2019-08-22drm/i915/psr: Make PSR registers relative to transcodersJosé Roberto de Souza
2019-08-20drm/i915/tgl: Updated Private PAT programmingMichel Thierry
2019-08-16drm/i915: Move gmbus definitions out of i915_reg.hDaniele Ceraolo Spurio
2019-08-16drm/i915: Move engine IDs out of i915_reg.hDaniele Ceraolo Spurio
2019-08-16drm/i915: Move i915_power_well_id out of i915_reg.hDaniele Ceraolo Spurio
2019-08-13drm/i915: Add _TRANS2()José Roberto de Souza
2019-08-13drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORTJosé Roberto de Souza
2019-08-08drm/i915/tgl: Fix the read of the DDI that transcoder is attached toJosé Roberto de Souza
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni
2019-08-01drm/i915/tgl: Add and use new DC5 and DC6 residency counter registersJosé Roberto de Souza
2019-07-31drm/i915/tgl: Tigerlake only has global MOCS registersMichel Thierry
generated by cgit (git 2.34.1) at 2025-05-29 15:59:35 +0000