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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)Author
2022-04-20drm/i915: program wm blocks to at least blocks required per lineVinod Govindapillai
2022-04-06drm/i915/adlp: Fix register corruption after DDI clock enablingImre Deak
2022-04-01drm/i915/display: Add HAS_MBUS_JOININGJosé Roberto de Souza
2022-03-30drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTLJosé Roberto de Souza
2022-03-21drm/i915: Remove total[] and uv_total[] from ddb allocationVille Syrjälä
2022-03-21drm/i915: Pre-calculate plane relative data rateVille Syrjälä
2022-03-21drm/i915: Tweak plane ddb allocation trackingVille Syrjälä
2022-03-18drm/i915: Rename pre-icl SAGV enable/disable functionsVille Syrjälä
2022-03-18drm/i915: Reject excessive SAGV block timeVille Syrjälä
2022-03-18drm/i915: Probe whether SAGV works on pre-iclVille Syrjälä
2022-03-18drm/i915: Rework SAGV block time probingVille Syrjälä
2022-03-18drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä
2022-03-09drm/i915: Remove leftover cnl SAGV block timeVille Syrjälä
2022-03-03drm/i915: Don't skip ddb allocation if data_rate==0Ville Syrjälä
2022-03-02drm/i915: Use str_enabled_disabled()Lucas De Marchi
2022-03-02drm/i915: Use str_yes_no()Lucas De Marchi
2022-02-28drm/i915/wm: use REG_FIELD_{PREP,GET} for PLANE_WM_BLOCKS_MASKJani Nikula
2022-02-24drm/i915/dg2: Tile 4 plane format supportStanislav Lisovskiy
2022-02-18drm/i915: Pimp icl+ sagv pre/post updateVille Syrjälä
2022-02-18drm/i915: Split pre-icl vs. icl+ SAGV hooks apartVille Syrjälä
2022-02-18drm/i915: Correctly populate use_sagv_wm for all pipesVille Syrjälä
2022-02-18drm/i915: Polish ilk+ wm register bitsVille Syrjälä
2022-02-18drm/i915: Clean up SSKPD/MLTR definesVille Syrjälä
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper
2022-02-16drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update()Ville Syrjälä
2022-02-16drm/i915: Use {active,scaled}_planes to compute ilk watermarksVille Syrjälä
2022-02-11drm/i915: Extract skl_allocate_plane_ddb()Ville Syrjälä
2022-02-11drm/i915: Introduce skl_plane_ddb_iterVille Syrjälä
2022-02-11drm/i915: Fix plane relative_data_rate calculationVille Syrjälä
2022-02-11drm/i915: Extract skl_ddb_entry_init()Ville Syrjälä
2022-02-11drm/i915: Drop pointless dev_priv argumentVille Syrjälä
2022-02-09drm/i915/pm: hide struct drm_i915_clock_gating_funcsJani Nikula
2022-02-08drm/i915: Fix mbus join config lookupVille Syrjälä
2022-02-08drm/i915: Fix dbuf slice config lookupVille Syrjälä
2022-02-07drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKLVille Syrjälä
2022-02-07drm/i915: Populate pipe dbuf slices more accurately during readoutVille Syrjälä
2022-02-07drm/i915: Allow !join_mbus cases for adlp+ dbuf configurationVille Syrjälä
2022-02-02drm/i915: Move GT registers to their own header fileMatt Roper
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi
2022-01-26drm/i915: Use single_enabled_crtc() in i9xx_update_wm()Ville Syrjälä
2022-01-26drm/i915: Use the correct plane source width in watermark calculationsVille Syrjälä
2022-01-26drm/i915: Fix up pixel_rate vs. clock confusion in wm calculationsVille Syrjälä
2022-01-26drm/i915: Don't allocate extra ddb during async flip for DG2Stanislav Lisovskiy
2022-01-26drm/i915: Use wm0 only during async flips for DG2Stanislav Lisovskiy
2022-01-26drm/i915: Pass plane to watermark calculation functionsStanislav Lisovskiy
2022-01-24drm/i915: Clean up pre-skl primary plane registersVille Syrjälä
2022-01-19drm/i915: Remove zombie async flip vt-d w/aVille Syrjälä
2022-01-18drm/i915: Use REG_BIT() & co. for universal plane bitsVille Syrjälä
2022-01-13drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*Jani Nikula
2022-01-11drm/i915/gt: Move engine registers to their own headerMatt Roper
generated by cgit (git 2.34.1) at 2025-03-26 04:06:58 +0000