Age | Commit message (Collapse) | Author |
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Currently unused, and rudimentary. Lots to figure out here still, but
this is sufficient for what disp will need.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Currently unused.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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disp is going to need to be able to create more specific dma objects
than was previously possible.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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The hardware dmaobj format completely changed in GF119, so these will
need a separate implementation.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Otherwise when nvc0- gains a bind() method (disp needs it), the fifo
engine will attempt to create a dma object for the push buffer, which
is unnecessary on fermi.
The only sane place to put these checks is in the bind method itself,
and have it unconditionally called from wherever it might be needed.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Simplifies things a little, and currently no reason to need
chipset-specific dmaobj constructors.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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We don't need to pull the page address out of the page tables on nv4x
chips that have a real GART.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Future code will use the object class rather than chipset checks in order to
identify available channel features.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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This is a HUGE commit, but it's not nearly as bad as it looks - any problems
can be isolated to a particular chipset and engine combination. It was
simply too difficult to port each one at a time, the compat layers are
*already* ridiculous.
Most of the changes here are simply to the glue, the process for each of the
engine modules was to start with a standard skeleton and copy+paste the old
code into the appropriate places, fixing up variable names etc as needed.
v2: Marcin Slusarz <marcin.slusarz@gmail.com>
- fix find/replace bug in license header
v3: Ben Skeggs <bskeggs@redhat.com>
- bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and
left no space for kernel's requirements during GEM pushbuf submission.
- fix duplicate assignments noticed by clang
v4: Marcin Slusarz <marcin.slusarz@gmail.com>
- add sparse annotations to nv04_fifo_pause/nv04_fifo_start
- use ioread32_native/iowrite32_native for fifo control registers
v5: Ben Skeggs <bskeggs@redhat.com>
- rebase on v3.6-rc4, modified to keep copy engine fix intact
- nv10/fence: unmap fence bo before destroying
- fixed fermi regression when using nvidia gr fuc
- fixed typo in supported dma_mask checking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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