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Future work will be headed in the way of separating the policy supplied by
the nouveau drm module from the mechanisms provided by the driver core.
There will be a couple of major classes (subdev, engine) of driver modules
that have clearly defined tasks, and the further directory structure change
is to reflect this.
No code changes here whatsoever, aside from fixing up a couple of include
file pathnames.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92
This fixes some reclocking issues on my newly acquired nv92
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Idea from Martin Peres, different implementation by me.
v2: Martin Peres:
- fix mast calculation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
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calc_mclk() returns zero on success and negative on failure but clk is
a u32.
v2: Martin Peres:
- clk should be an int, not a u32
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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We don't need more than the line id to determine the PWM controller, and
the GPIO interfaces are about to change somewhat.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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More work needs to be done on supporting the different memory types.
v2 (Ben Skeggs):
- fixed up conflicts from not having pausing patch first
- restructured code somewhat to fit with how all the other code works
- fixed bug where incorrect mpll_ctrl could get set sometimes
- removed stuff that's cargo-culted from the binary driver
- merged nv92+ display disable into hwsq
- fixed incorrect opcode 0x5f magic at end of ucode
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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read_pll_ref() needs to take into account the refclk src bits in 0xc040 on
some chipsets, it wasn't doing this.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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This area is horrifically complicated on these chipsets, and it's likely we
will need at least a few more tweaks yet.
Oh yes, and it's completely disabled on IGPs for the moment. From traces,
things look potentially different there yet again. Sigh...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Many of the nv50 cards have their shader and/or memory pll
disabled at some stage.
This patch addresses those cases, so that the function
returns the correct frequency.
When the shader pll is disabled, the blob reports 2*core clock
Whereas for memory, the data stored in the vbios. This action
is incorrect as some vbioses store a clock value that is less
than the refference clock of the pll.
Thus we are reporting the reff_clk as it is the frequency the
pll actually operates
v2 - Convert NV_INFO() messages to NV_DEBUG()
Provide more information in the actuall message
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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This will end up quite different, it makes sense for it to be completely
separate.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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On certain boards, there's BIOS scripts and memory timings that need to
be modified with the memclk. Just pass in the entire perflvl struct and
let the chipset-specific code decide what to do.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Guarded by a module parameter for the moment, read the code for the
magic value which enables it.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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This will make nouveau_pm attempt to report the card's current performance
level both during bootup, and through sysfs.
This is a very initial implementation, and can be improved a *lot*
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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