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path: root/drivers/gpu/drm
AgeCommit message (Expand)Author
2018-11-30drm/i915/psr: Get pipe id following atomic guidelinesJosé Roberto de Souza
2018-11-30drm/i915/selftests: Fix live_workarounds to actually do resetsTvrtko Ursulin
2018-11-30drm/i915/selftests: Extract spinner codeTvrtko Ursulin
2018-11-30drm/i915/icl: Remove Wa_1604302699Tvrtko Ursulin
2018-11-30drm/i915: Remove whitelist application from ringbuffer backendTvrtko Ursulin
2018-11-30drm/i915: Fixup stub definitions for intel_opregion_suspend|resumeChris Wilson
2018-11-29drm/i915/fec: Disable FEC state.Anusha Srivatsa
2018-11-29i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa
2018-11-29drm/i915/fec: Set FEC_READY in FEC_CONFIGURATIONAnusha Srivatsa
2018-11-29i915/dp/fec: Add fec_enable to the crtc state.Anusha Srivatsa
2018-11-29drm/i915/dsc: Enable and disable appropriate power wells for VDSCManasi Navare
2018-11-29drm/i915/dp: Disable DSC in source by disabling DSS CTL bitsManasi Navare
2018-11-29drm/i915/dp: Configure Display stream splitter registers during DSC enableManasi Navare
2018-11-29drm/i915/dp: Populate DSC PPS SDP and send PPS infoframesManasi Navare
2018-11-29drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare
2018-11-29drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enablingManasi Navare
2018-11-29drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSIManasi Navare
2018-11-29drm/i915/dp: Enable/Disable DSC in DP SinkGaurav K Singh
2018-11-29drm/i915/dsc: Compute Rate Control parameters for DSCGaurav K Singh
2018-11-29drm/i915/dsc: Define & Compute VESA DSC paramsGaurav K Singh
2018-11-29drm/i915/dp: Do not enable PSR2 if DSC is enabledManasi Navare
2018-11-29drm/i915/dp: Compute DSC pipe config in atomic checkManasi Navare
2018-11-29drm/i915/dp: Add DSC params and DSC config to intel_crtc_stateManasi Navare
2018-11-29drm/i915: Decouple SKL stride units from intel_fb_stride_alignment()Ville Syrjälä
2018-11-29drm/i915: Make sure fb gtt offsets stay within 32bitsVille Syrjälä
2018-11-28drm/i915: Pass the plane to icl_program_input_csc_coeff()Ville Syrjälä
2018-11-28drm/i915: Rename the confusing 'plane_id' to 'color_plane'Ville Syrjälä
2018-11-28drm/i915: Commit skl+ planes in an order that avoids ddb overlapsVille Syrjälä
2018-11-28drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+Ville Syrjälä
2018-11-28drm/i915: Don't pass dev_priv around so muchVille Syrjälä
2018-11-28drm/i915: Clean up skl+ vs. icl+ watermark computationVille Syrjälä
2018-11-28drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()Ville Syrjälä
2018-11-28drm/i915: Remove some useless zeroing on skl+ wm calculationsVille Syrjälä
2018-11-28drm/i915: Fix latency==0 handling for level 0 watermark on skl+Ville Syrjälä
2018-11-28drm/i915: Pass the new crtc_state to ->disable_plane()Ville Syrjälä
2018-11-28drm/i915: Introduce crtc_state->update_planes bitmaskVille Syrjälä
2018-11-28drm/i915: Move single buffered plane register writes to the endVille Syrjälä
2018-11-28drm/i915: Reorganize plane register writes to make them more atomicVille Syrjälä
2018-11-28drm/i915: Mark up early pre-production KabylakesChris Wilson
2018-11-27drm/dsc: Add helpers for DSC picture parameter set infoframesManasi Navare
2018-11-27drm/dsc: Modify DRM helper to return complete DSC color depth capabilitiesManasi Navare
2018-11-27drm/i915: Skip engine serialisation for no-op seqno resetChris Wilson
2018-11-26drm/i915/ringbuffer: 2-step restartChris Wilson
2018-11-23drm/i915: Cache the error stringChris Wilson
2018-11-22drm/i915/hsw: Drop the stereo 3D enabled check in psr_compute_config()José Roberto de Souza
2018-11-22drm/i915: Keep PSR disabled after a driver reload after a PSR errorJosé Roberto de Souza
2018-11-22drm/i915: Disable PSR when a PSR aux error happenJosé Roberto de Souza
2018-11-22drm/i915: Do not enable PSR in the next modeset after a errorJosé Roberto de Souza
2018-11-22drm/i915: Check PSR errors instead of retrain while PSR is enabledJosé Roberto de Souza
2018-11-22drm/i915: Avoid a full port detection in the first eDP short pulseJosé Roberto de Souza
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