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path: root/drivers/gpu/drm
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2023-10-04drm/i915: s/dev_priv/i915/ in the shared_dpll codeVille Syrjälä
Do a s/dev_priv/i915/ pass over the shared_dpll code to get the variable names into sync with modern standards. v2: Rebase Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-5-ville.syrjala@linux.intel.com
2023-10-04drm/i915: Introduce for_each_shared_dpll()Ville Syrjälä
No one really cares how we store the shared_dplls. Currently it happens to be an array, but we could change that to a more flexible scheme at some point. Hide the implementation details behind an iterator macro. The slight downside is the pll variable moving out of the loop scope, but maybe someday soon we'll start to convert everything over to having declarations within for-statements... Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-4-ville.syrjala@linux.intel.com
2023-10-04drm/i915: Decouple I915_NUM_PLLS from PLL IDsVille Syrjälä
Stop assuming the size of PLL ID based bitmask is restricted to I915_NUM_PLLS bits. This is the last thing coupling the two things together and thus artificially limiting PLL IDs. We could just pass any arbitrary (large enough) size to for_each_set_bit() and be done with it, but the WARN requiring the caller to not pass in a bogus bitmask seems potentially useful to keep around. So let's just calculate the full bitmask on the spot. And while at it let's assert that the PLL IDs will fit into the bitmask we use for them. TODO: could also get rid of I915_NUM_PLLS entirely and just dynamically allocate i915->shared_dplls[] and state->shared_dpll[]. But that would involve error handling in the modeset init path. Uff. v2: Warn about conflicting PLL IDs (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-3-ville.syrjala@linux.intel.com
2023-10-04drm/i915: Stop requiring PLL index == PLL IDVille Syrjälä
There's no good reason to keep around this PLL index == PLL ID footgun. Get rid of it. Both i915->shared_dplls[] and state->shared_dpll[] are indexed by the same thing now, which is just the index we get at initialization from dpll_mgr->dpll_info[]. The rest is all about PLL IDs now. v2: Add pll->index to mimic drm_crtc & co. Remove the comment saying ID should match the index v3: s/i/pll->index/ in debugfs loop (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-2-ville.syrjala@linux.intel.com
2023-10-04drm/i915: separate subplatform init and runtime feature initJani Nikula
Adjusting ->port_mask does not belong in intel_device_info_subplatform_init(), but rather intel_display_device_info_runtime_init(). Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1035800e623e13d5e7baf1215b07e7cdad5eb764.1696336887.git.jani.nikula@intel.com
2023-10-04drm/i915: separate display runtime info initJani Nikula
Move display related functionality from intel_device_info_runtime_init() to intel_display_device_info_runtime_init() and call the latter from the top level. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a2226a47a4450e75d867c2ac48665b387af0e42d.1696336887.git.jani.nikula@intel.com
2023-10-04drm/i915: move display info related macros to displayJani Nikula
Anything looking at display (runtime) info should be under display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/41b53870ffa7bd41ccc337616c756c69326f05cf.1696336887.git.jani.nikula@intel.com
2023-10-04drm/i915: convert INTEL_DISPLAY_ENABLED() into a functionJani Nikula
There's no need for this to be a macro. Add some documentation too. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/480b9b697b2ffa0c8677115bd443ba633801c6c1.1696336887.git.jani.nikula@intel.com
2023-10-03drm/i915/lnl: update the supported plane formats with FBCVinod Govindapillai
FBC is supported with RGB32 8:8:8:8 with or without alpha Bspec: 68904, 69560 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230922133003.150578-3-vinod.govindapillai@intel.com
2023-10-03drm/i915/lnl: possibility to enable FBC on first three planesVinod Govindapillai
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding register writes (Matt) - Update the subject to reflect that fbc can be enabled only in the first three planes (Matt) v3: - use icl_is_hdr_plane(), use wrapper macro for plane binding register access, comments update and patch split (Ville) v4: - update to the plane binding register access macro Bspec: 69560 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230922133003.150578-2-vinod.govindapillai@intel.com
2023-10-02drm/i915: Abstract display info away during probeRodrigo Vivi
The goal is to have this function ready for Xe to use directly. So, let's use the available macro. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230929205023.1202735-1-rodrigo.vivi@intel.com
2023-10-02drm/i915/display: Include i915_active header in frontbuffer tracking codeJouni Högander
Intel frontbuffer tracking code is using i915_active functions -> include i915_active.h directly instead of relying getting indirectly included. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230929112047.1151914-1-jouni.hogander@intel.com
2023-09-29drm/i915/display: add I915 conditional build to vlv_dsi_pll.hJani Nikula
Add stubs for !I915. Not all the functions need to be stubbed. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/930c8d332d425a54dae7af16aed26ec293f80afd.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_tv.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/290e555ac87ea11cd6021c1338b75ad64c42ae98.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_sdvo.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/c34ea1f470590488acf40512da3892ca153f482a.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_dvo.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/d43b27742297083b37d52222c4bb72b062ef4967.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to g4x_hdmi.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/ba2eea7ac081d0858a573062f197e00f3b186faf.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to i9xx_wm.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/bf15b14d3d060fdb256c78d4b8514d642a8958e6.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to vlv_dsi.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/9f538824f15096b0c1444ee50d175a0a22d7bd5e.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_crt.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/89a6daca98f87ed1a8a54367a977f146216330d2.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_dpio_phy.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/978bc7263e8de10ffc1ef16086341dd629347c8e.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to g4x_dp.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/ba92fc1dee1f71018179dbe10b91982c9c93e7e6.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_overlay.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/45a127d37816ac97dfe493beeed060e323047014.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_sprite.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/b9680203b0b93dc3472260d7e4128984e533b421.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_pch_display.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/02de0089de58c9fb19b6b56121f6c917f51b4561.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_pch_refclk.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/4359b34cbcff6199b5e42b5311c815aa6f4a167c.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_lpe_audio.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/7c10d8c4a2a628cba17b3b0f89b657dfbc91eaa9.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to i9xx_plane.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/4ad1864c66adcf691906c37b554f640d04069fb2.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to hsw_ips.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/04469b92be51b8394d74a508174f041aa7e011e8.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915/display: add I915 conditional build to intel_lvds.hJani Nikula
Add stubs for !I915. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/f06a88a69b7e326ff0914baca5e6a0e5f06e1867.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915: define I915 during i915 driver buildJani Nikula
The xe driver will reuse i915 display code by compiling it separately as part of xe. We'll want to be able to distinguish between building the i915 display code for i915 and xe. Define I915 when building i915. Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/97558201836115b91cbe32840239df855d0c2e4c.1694514689.git.jani.nikula@intel.com
2023-09-29drm/i915: Update DRIVER_DATE to 20230929Jani Nikula
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-09-29drm/i915: Warn on if set frontbuffer return value is not NULL on releaseJouni Högander
i915_gem_object_set_frontbuffer returns set frontbuffer pointer. When we are releasing frontbuffer we are clearing the pointer from the object. Warn on if return value is not null. v3: Check i915_gem_object_set_frontbuffer return value separately v2: Instead of ignoring do drm_WARN_ON Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230928082924.164720-1-jouni.hogander@intel.com
2023-09-28drm/i915/fdi: Recompute state for affected CRTCs on FDI linksImre Deak
Recompute the state of all CRTCs on an FDI link during a modeset that may be affected by the modeset of other CRTCs on the same link. This ensures that each CRTC on the link maximizes its BW use (after another CRTC is disabled). In practice this means recomputing pipe B's config on IVB if pipe C gets disabled. v2: - Add the change recomputing affected CRTC states in a separate patch. (Ville) v3: (Ville) - Constify old and new crtc states. - Check for fused off pipe C. - Fix new vs. old crtc state mixup. - Drop check for pipe C's enabled state. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-12-imre.deak@intel.com
2023-09-28drm/i915/fdi: Improve FDI BW sharing between pipe B and CImre Deak
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI lanes. Make the BW sharing more dynamic by trying to reduce pipe B's link bpp in this case, until pipe B uses only up to 2 FDI lanes. For this instead of the encoder compute config retry loop - which reduced link bpp only for the encoder's pipe - reduce the maximum link bpp for pipe B/C as required after all CRTC states are computed and recompute the CRTC states with the new bpp limit. Atm, all FDI encoder's compute config function returns an error if a BW constrain prevents increasing the pipe bpp value. The corresponding crtc_state->bw_constrained check can be replaced with checking crtc_state->max_link_bpp_x16, add TODO comments for this. SDVO is an exception where this case is only handled in the outer config retry loop, failing the modeset with a WARN, add a FIXME comment to handle this in the encoder code similarly to other encoders. v2: - Don't assume that a CRTC is already in the atomic state, while reducing its link bpp. - Add DocBook description to intel_fdi_atomic_check_link(). v3: - Enable BW management for FDI links in a separate patch. (Ville) v4: (Ville) - Fail the SDVO encoder config computation if it doesn't support the link bpp limit. - Add TODO: comments about checking link_bpp_x16 instead of bw_constrained. v5: - Replace link bpp limit check with a FIXME: comment in intel_sdvo_compute_config(). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [Amended commit message wrt. changes in v5] Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-11-imre.deak@intel.com
2023-09-28drm/i915: Add helpers for BW management on shared display linksImre Deak
At the moment a modeset fails if the config computation of a pipe can't fit its required BW to the available link BW even though the limitation may be resolved by reducing the BW requirement of other pipes. To improve the above this patch adds helper functions checking the overall BW limits after all CRTC states have been computed. If the check fails the maximum link bpp for a selected pipe will be reduced and all the CRTC states will be recomputed until either the overall BW limit check passes, or further bpp reduction is not possible (because all pipes/encoders sharing the link BW reached their minimum link bpp). Atm, the MST encoder allocates twice the required BW for YUV420 format streams. A follow-up patchset will fix that, add a code comment about this. This change prepares for upcoming patches enabling the above BW management on FDI and MST links. v2: - Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani) v3: - Add the helper functions in a separate patch. (Ville) - Add the functions to intel_link_bw.c instead of intel_atomic.c (Ville) - Return -ENOSPC instead of -EINVAL to userspace in case of a link BW limit failure. v4: - Make intel_atomic_check_config() static. v5: (Ville) - Rename intel_link_bw_limits::min_bpp_pipes to min_bpp_reached_pipes and intel_link_bw_reset_pipe_limit_to_min() to intel_link_bw_set_min_bpp_for_pipe(). - Rename pipe_bpp to link_bpp in intel_link_bw_reduce_bpp(). - Add FIXME: comment about MST encoder's YUV420 BW allocation and tracking the link bpp limit accordingly. v6: - Move intel_link_bw_compute_pipe_bpp() to intel_fdi.c (Ville) - WARN_ON(BIT(pipe) & min_bpp_reached_pipes) in intel_link_bw_set_bpp_limit_for_pipe(). (Ville) - Rename intel_link_bw_set_min_bpp_for_pipe() to intel_link_bw_set_bpp_limit_for_pipe() and intel_link_bw_limits::min_bpp_reached_pipes to bpp_limit_reached_pipes. (Ville) - Remove unused header includes. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-10-imre.deak@intel.com
2023-09-28drm/i915: Factor out a helper to check/compute all the CRTC statesImre Deak
Factor out intel_atomic_check_config() to check and compute all the CRTC states. This will be used by a follow up patch to recompute/check the state until required by BW limitations between CRTCs. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-9-imre.deak@intel.com
2023-09-28drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak
Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late() to clarify when the function can be called (vs. intel_modeset_pipes_in_mask_early()). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-8-imre.deak@intel.com
2023-09-28drm/i915: Add helper to modeset a set of pipesImre Deak
Add intel_modeset_pipes_in_mask_early() to modeset a provided set of pipes, used in a follow-up patch. As opposed to intel_modeset_all_pipes() which modesets only the active pipes - others don't requiring programming the HW - modeset all enabled pipes in intel_modeset_pipes_in_mask_early() which may need to recompute their state even if they are not active (that is in the DPMS off state). While at it add DocBook descriptions for the two exported functions. v2: - Add a flag controlling if active planes are force updated as well. - Add DockBook descriptions. v3: - For clarity use _early/_late suffixes for the exported functions instead of the update_active_planes parameter. (Ville) v4: - In intel_modeset_pipes_in_mask_early() update only the crtc flags relevant to the early phase. (Ville) - Rename intel_modeset_all_pipes() in a separate patch. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-7-imre.deak@intel.com
2023-09-28drm/i915/dp: Limit the output link bpp in DSC modeImre Deak
Limit the output link bpp in DSC mode to the link_config_limits link.min_bpp_x16 .. max_bpp_x16 range the same way it's done in non-DSC mode. Atm this doesn't make a difference, the link bpp range being 0 .. max pipe bpp, but a follow-up patch will need a way to reduce max link bpp below its current value. v2: - Add to_bpp_int_roundup() instead of open coding it. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-6-imre.deak@intel.com
2023-09-28drm/i915/dp: Update the link bpp limits for DSC modeImre Deak
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp range, while in DSC mode it can be set in 1/16 bpp steps to any value up to the maximum pipe bpp. Update the limits accordingly in both modes to prepare for a follow-up patch which may need to reduce the max link bpp value and starts to check the link bpp limits in DSC mode as well. While at it add more detail to the link limit debug print and print it also for DSC mode. v2: - Add to_bpp_frac_dec() instead of open coding it. (Jani) v3: (Ville) - Add BPP_X16_FMT / BPP_X16_ARG. - Add TODO: comment about initializing the DSC link bpp limits earlier. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-5-imre.deak@intel.com
2023-09-28drm/i915/dp: Skip computing a non-DSC link config if DSC is neededImre Deak
Computing the non-DSC mode link config is redundant once it's determined that DSC will be needed, so skip computing it. In a follow-up patch this simplifies setting the link limits which are dependent on the DSC vs. non-DSC mode. While at it sanitize the debug print about the MST DSC fallback path, making it similar to the SST DSC one. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-4-imre.deak@intel.com
2023-09-28drm/i915/dp: Track the pipe and link bpp limits separatelyImre Deak
A follow-up patch will need to limit the output link bpp both in the non-DSC and DSC configuration, so track the pipe and link bpp limits separately in the link_config_limits struct. Use .4 fixed point format for link bpp matching the 1/16 bpp granularity in DSC mode and for now keep this limit matching the pipe bpp limit. v2: (Jani) - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them. - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16. Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-3-imre.deak@intel.com
2023-09-28drm/i915/dp: Factor out helpers to compute the link limitsImre Deak
Factor out helpers that DP / DP_MST encoders can use to compute the link rate/lane count and bpp limits. A follow-up patch will call these to recalculate the limits if DSC compression is required. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-2-imre.deak@intel.com
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä
Normally we could be in a deep PkgC state all the way up to the point when DSB starts its execution at the transcoders undelayed vblank. The DSB will then have to wait for the hardware to wake up before it can execute anything. This will waste a huge chunk of the vblank time just waiting, and risks the DSB execution spilling into the vertical active period. That will be very bad, especially when programming the LUTs as the anti-collision logic will cause DSB to corrupt LUT writes during vertical active. To avoid these problems we can instruct the DSB to pre-wake the display engine on a specific scanline so that everything will be 100% ready to go when we hit the transcoder's undelayed vblank. One annoyance is that the scanline is specified as just that, a single scanline. So if we happen to start the DSB execution after passing said scanline no DEwake will happen and we may drop back into some PkgC state before reaching the transcoder's undelayed vblank. To prevent that we'll use the "force DEwake" bit to manually force the display engine to stay awake. We'll then have to clear the force bit again after the DSB is done (the force bit remains effective even when the DSB is otherwise disabled). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-18-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-09-27drm/i915: Introduce intel_crtc_scanline_to_hw()Ville Syrjälä
Add a helper to convert our idea of a scanline to the hw's idea of the same scanline (ie. apply crtc->scanline_offset in reverse). We'll need this to tell the DSB do stuff on a specific scanline. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-17-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-09-27drm/i915: Introduce skl_watermark_max_latency()Ville Syrjälä
The DSB code will want to know the maximum PkgC latency it has to contend with. Add a helper to expose that information. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-16-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-09-27drm/i915/dsb: Evade transcoder undelayed vblank when using DSBVille Syrjälä
We want to start the DSB execution from the transcoder's undelayed vblank, so in order to guarantee atomicity with the all the other mmio register writes we need to evade both vblanks. Note that currently we don't add any vblank delay, so this is effectively a nop. But in the future when we start to program double buffered registers from the DSB we'll need to delay the pipe's vblank to provide the register programming "window2" for the DSB. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-15-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-09-27drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä
The DSB has problems writing the legacy LUT. The two workarounds I've discoverted are: - write each entry twice back to back - use non-posted writes Let's use non-posted writes as that seems a bit more standard. TODO: measure which is faster Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-14-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-09-27drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä
Loading LUTs with the DSB outside of vblank doesn't really work due to the palette anti-collision logic. Apparently the DSB register writes don't get stalled like CPU mmio writes do and instead we end up corrupting the LUT entries. Disabling the anti-collision logic would allow us to successfully load the LUT outside of vblank, but presumably that risks the LUT reads from the scanout (temporarily) getting corrupted data from the LUT instead. The anti-collision logic isn't active during vblank so that is when we can successfully load the LUT with the DSB. That is what we want to do anyway to avoid tearing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-13-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
generated by cgit (git 2.34.1) at 2025-04-27 11:46:52 +0000