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path: root/drivers/gpu/drm
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2023-08-07drm/amd/display: Add vendor Id for referenceMike Hsieh
Add a new vendor ID code for reference Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mike Hsieh <mike.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN314Leo Chen
[Why & How] HDMI TMDS does not have ODM support. Filtering 420 modes that exceed the 4096 FMT limitation on DCN314 will resolve intermittent corruptions issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31Leo Chen
[Why & How] HDMI TMDS does not have ODM support. Filtering 420 modes that exceed the 4096 FMT limitation on DCN31 will resolve intermittent corruptions issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Revert "drm/amd/display: Read down-spread percentage from ↵Leo Chen
lut to adjust dprefclk." [Why & How] Revert commit 6917b0b71171 ("drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.") This change was causing 240hz display to not light up after s0i3. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: do not treat clip_rect size change as a scaling changeWenjing Liu
[why] With previous ODM + MPO policy we will only allocate pipes when MPO plane has intersection with current ODM slice. With this policy we have to indicate scaling change when plane clip is updated in case plane clip change causes MPO plane to go in or out current ODM slice. With new ODM + MPO policy we allocate pipe independent from plane clip size so we no longer treat it as a scaling change. There no need to do a full update due to clip size change anymore. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: adjust visual confirm dpp height offset to be 1/240 of v ↵Wenjing Liu
addressable [why] For timing with large v addressable visual confirm is just too small. It is difficult to tell visually which DPP we are using. On the other hand with timing with small v addressable visual confirm is too large and covers the UI area. [how] We calculate visual confirm dpp height offset based on v addressable so it stays relatively the same height i.e. 1/240 verticle portion of the screen. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: update add plane to context logic with a new algorithmWenjing Liu
[why] Preivous algorithm for finding an optimal idle pipe for a new plane was implemented to handle dynamic pipe allocation when MPO plane moves from one ODM slice to the other. Now pipe allocation is more static so it no longer depends on the MPO plane's position. We are simplifying our logic and remove unnecessary handling in our code. [how] Apply a new simplified version of pipe resource allocation logic to reduce unnecessary flip delay caused by swapping secondary dpp pipe to other MPC blending tree. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: always acquire MPO pipe for every blending treeWenjing Liu
[why] We only acquire MPO pipe for blending tree where the plane clip will be rendered. If an MPO plane is outside current ODM slice rect, we will skip pipe allocation. With new programming policy we want to allocate pipes for every ODM slice blending tree even for those whose ODM slice rect doesn't intersect with plane clip. This is aligned with DML validation so the pipe topology is programmed independently from the plane's position and dst plane size. [how] - Remove the logic to allocate pipe only when the MPO plane intersects with ODM slice and replace with the new logic to always allocate pipes. - Remove the logic to tear down ODM configuration in favor for supporting secondary MPO planes. - Remove the logic to use full update when MPO goes accross ODM slice boundary. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: support plane clip with zero recout sizeWenjing Liu
[why] If plane clip is outside current pipe's ODM slice rect, our logic will fail validation because we assume that when a pipe is acquired to support a plane clip, it must blend some portion of the plane on the screen. This assumption needs to be changed. When a pipe is acquired to render the plane, we are now allowing it to support a case where it can take minimum viewport and draw with zero recout size when the plane clip is outside current ODM slice rect. The reason is that we want to allocate and get the pipe pre-programmed so it is ready to be rendered when user moves the plane over to the current ODM slice with a fast update. Whereas with the existing solution when user moves the plane over, we will need to allocate a pipe as needed and power it up and program it through a full update. This not only impacts the user experience with unnecessary delay of a frame but also doesn't generate any benefit to the user because DML doesn't support it. DML will invalidate based on worst case scenario and it doesn't depend on the plane location. So having our programming sequence support such dynamic pipe allocation is not meaningful anyway. [how] In build scaler params allow recout to be zero size and if viewport is smaller than minimum, set minimum viewport size. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Use DTBCLK as refclk instead of DPREFCLKAustin Zheng
[Why] Flash of corruption observed when UCLK switching after transitioning from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config Scenario where DPREFCLK is required instead of DTBCLK is not expected [How] Always set the DTBCLK source as DTBCLK0 Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Set Stream Update Flags in commit_state_no_checkAustin Zheng
[Why] Front-end would be programmed using the stream update flags set from the previous update and the full update should be triggered whenever commit_state_no_check gets called. [How] Set all stream update flags before programming the front-end Clear all flags that got set to avoid redundant programming Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Make mpc32 functions available to future DCNsWesley Chalmers
Make the mpc32 functions available for future DCNs to use Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wesley Chalmers <wesley.chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Fix a bug when searching for insert_above_mpccWesley Chalmers
[WHY] Currently, when insert_plane is called with insert_above_mpcc parameter that is equal to tree->opp_list, the function returns NULL. [HOW] Instead, the function should insert the plane at the top of the tree. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wesley Chalmers <wesley.chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Enable DPIA trace with DC debug maskStylon Wang
[Why] DPIA traces from DMUB is not enabled by default, which is less convenient to debug DPIA related issues because we have to resort to other means to enable DPIA trace. [How] Reuse existing DC debug mask to enable DPIA trace log from kernel command line. This makes debugging DPIA issues easier especially when system power state (suspend/reboot) is involved. To turn on DPIA trace, simply add "amdgpu.dcdebugmask=0x80" to kernel command line. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add interface to enable DPIA traceStylon Wang
[Why] DPIA traces from DMUB is not enabled by default, which is less convenient to debug DPIA related issues because we have to resort to other debug tools to enable DPIA trace. [How] Exposes interfaces to update trace mask from the DMUB GPINT commands. Also provides DC implementations to enable DPIA trace. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: fix a regression in blank pixel data caused by coding mistakeWenjing Liu
[why] There was unfortunately a coding mistake. It gets caught with an ultrawide monitor that requires ODM 4:1 combine. We are blanking or unblanking pixel data we are supposed to enumerate through all ODM pipes and program DPG for each of those pipes. However the coding mistake causes us to program only the first and last ODM pipes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: cleanup MES process level doorbellsShashank Sharma
MES allocates process level doorbells, but there is no userspace client to consume it. It was only being used for the MES ring tests (in kernel), and was written by kernel doorbell write. The previous patch of this series has changed the MES ring test code to use kernel level MES doorbells. This patch now cleans up the process level doorbell allocation code which is not required. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: use doorbell mgr for MES kernel doorbellsShashank Sharma
This patch: - Removes the existing doorbell management code, and its variables from the doorbell_init function, it will be done in doorbell manager now. - uses the doorbell page created for MES kernel level needs (doorbells for MES self tests) - current MES code was allocating MES doorbells in MES process context, but those were getting written using kernel doorbell calls. This patch instead allocates a MES kernel doorbell for this (in add_hw_queue). V2: Create an extra page of doorbells for MES during kernel doorbell creation (Alex) V4: Move MES doorbell size and page offset objects in this patch from patch 6. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: remove unused functions and variablesShashank Sharma
This patch removes some variables and functions from KFD doorbell handling code, which are no more required since doorbell manager is handling doorbell calculations. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: ensure async flips are only accepted for fast updatesHamza Mahfooz
We should be checking to see if async flips are supported in amdgpu_dm_atomic_check() (i.e. not dm_crtc_helper_atomic_check()). Also, async flipping isn't supported if a plane's framebuffer changes memory domains during an atomic commit. So, move the check from dm_crtc_helper_atomic_check() to amdgpu_dm_atomic_check() and check if the memory domain has changed in amdgpu_dm_atomic_check(). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2733 Fixes: c1e18c44dc7f ("drm/amd/display: only accept async flips for fast updates") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: use doorbell mgr for kfd process doorbellsShashank Sharma
This patch: - adds a doorbell object in kfd pdd structure. - allocates doorbells for a process while creating its queue. - frees the doorbells with pdd destroy. - moves doorbell bitmap init function to kfd_doorbell.c PS: This patch ensures that we don't break the existing KFD functionality, but now KFD userspace library should also create doorbell pages as AMDGPU GEM objects using libdrm functions in userspace. The reference code for the same is available with AMDGPU Usermode queue libdrm MR. Once this is done, we will not need to create process doorbells in kernel. V2: - Do not use doorbell wrapper API, use amdgpu_bo_create_kernel instead (Alex). - Do not use custom doorbell structure, instead use separate variables for bo and doorbell_bitmap (Alex) V3: - Do not allocate doorbell page with PDD, delay doorbell process page allocation until really needed (Felix) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felilx.Kuehling@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: use doorbell mgr for kfd kernel doorbellsShashank Sharma
This patch: - adds a doorbell bo in kfd device structure. - creates doorbell page for kfd kernel usages. - updates the get_kernel_doorbell and free_kernel_doorbell functions accordingly V2: Do not use wrapper API, use direct amdgpu_create_kernel(Alex) V3: - Move single variable declaration below (Christian) - Add a to-do item to reuse the KGD kernel level doorbells for KFD for non-MES cases, instead of reserving one page (Felix) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Read replay data from sinkBhawanpreet Lakha
Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add Freesync Panel DM codeBhawanpreet Lakha
We need certain conditions for replay to be enabled, so create an interface in DM to enable/disable replay. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/pm: update smu_v13_0_6 message vf flagYang Wang
v1: Enable following message in vf mode. - PPSMC_MSG_GetMinGfxclkFreqquency - PPSMC_MSG_GetMaxGfxclkFreqquency - PPSMC_MSG_GetMinDpmFreq - PPSMC_MSG_GetMaxDpmFreq these message will cause pp_dpm_* device node not work properly. v2: the following message is disabled in VF mode. (since pmfw 85.69.0) - PPSMC_MSG_EnableAllSmuFeatures Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Report Missing MES Firmware Versions with SysfsOri Messinger
Added missing MES firmware versions to the 'fw_version' sysfs directory, they should now exist as a files named "mes_fw_version" and "mes_kiq_fw_version" found at: /sys/class/drm/cardX/device/fw_version/mes_fw_version /sys/class/drm/cardX/device/fw_version/mes_kiq_fw_version Where X is the card number, and the version is displayed in hexadecimal. Signed-off-by: Ori Messinger <ori.messinger@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: get absolute offset from doorbell indexShashank Sharma
This patch adds a helper function which converts a doorbell's relative index in a BO to an absolute doorbell offset in the doorbell BAR. V2: No space between the variable name doc (Luben) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/pm: Fix SMU v13.0.6 energy reportingLijo Lazar
Energy counter should be reported in units of 15.259 uJ. Don't apply any conversion. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: create kernel doorbell pagesShashank Sharma
This patch: - creates a doorbell page for graphics driver usages. - adds a few new varlables in adev->doorbell structure to keep track of kernel's doorbell-bo. - removes the adev->doorbell.ptr variable, replaces it with kernel-doorbell-bo's cpu address. V2: - Create doorbell BO directly, no wrappe functions (Alex) - no additional doorbell structure (Alex, Christian) - Use doorbell_cpu_ptr, remove ioremap (Christian, Alex) - Allocate one extra page of doorbells for MES (Alex) V4: Move MES doorbell base init into MES related patch (Christian) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Use nbio callback for nv and soc21Lijo Lazar
Make the new ascis to follow nbio callback method to get pcie replay count. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/pm: fix variable dereferenced issue in amdgpu_device_attr_create()Yang Wang
- fix variable ('attr') dereferenced issue. - using condition check instead of BUG_ON(). Fixes: 4e01847c38f7 ("drm/amdgpu: optimize amdgpu device attribute code") Cc: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Add pci replay count to nbio v7.9Lijo Lazar
Add implementation to get pcie replay count for nbio v7.9. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: initialize ttm for doorbellsShashank Sharma
This patch initialzes the ttm resource manager for doorbells. V2: Do not round up doorbell size (Alex) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: accommodate DOMAIN/PL_DOORBELLAlex Deucher
This patch adds changes: - to accommodate the new GEM domain for DOORBELLs - to accommodate the new TTM PL for DOORBELLs in order to manage doorbell pages as GEM object. V2: Addressed reviwe comments from Christian - drop the doorbell changes for pinning/unpinning - drop the doorbell changes for dma-buf map - drop the doorbell changes for sgt - no need to handle TTM_PL_FLAG_CONTIGUOUS for doorbell - add caching type for doorbell V3: - Removed unrelated empty line (Christian) - Add PL_DOORBELL in mem_type_to_domain() as well (Alex) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
2023-08-07drm/amdkfd: Sign-extend TMA address in trap handlerJay Cornwall
SMEM instructions can reach addresses above 47 bits but require bit 47 to be sign-extended through bits [63:48]. This allows the TMA to be relocated in a following patch. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdkfd: Relocate TBA/TMA to opposite side of VM holeJay Cornwall
The TBA and TMA, along with an unused IB allocation, reside at low addresses in the VM address space. A stray VM fault which hits these pages must be serviced by making their page table entries invalid. The scheduler depends upon these pages being resident and fails, preventing a debugger from inspecting the failure state. By relocating these pages above 47 bits in the VM address space they can only be reached when bits [63:48] are set to 1. This makes it much less likely for a misbehaving program to generate accesses to them. The current placement at VA (PAGE_SIZE*2) is readily hit by a NULL access with a small offset. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdkfd: Sync trap handler binaries with sourceJay Cornwall
Some changes have been lost during rebases. Rebuild sources. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: don't modify num_doorbells for mesShashank Sharma
This patch removes the check and change in num_kernel_doorbells for MES, which is not being used anywhere by MES code. V2: Fixed checkpatch warnings. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Add pcie replay count callback to nbioLijo Lazar
Add a callback in nbio to get pcie replay count. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Promote DC to 2.3.245Aric Cyr
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07Revert "drm/amd/display: Implement zpos property"Nicholas Choi
This reverts commit 5b29369b5488d54e466ef7c6a2020a4efc1d854f. This patch causes IGT test case 'kms_atomic@plane-immutable-zpos' to fail on AMDGPU hardware. Cc: Joshua Ashton <joshua@froggi.es> Signed-off-by: Nicholas Choi <Nicholas.Choi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Implement interface for notify cursor support changeAlvin Lee
[Description] Add new interface for notifying OS of cursor support changes Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: Prefer pr_err/_warn/_notice over printk in amdgpu_atpx_handler.cSrinivasan Shanmugam
Fixes the following style issues: ERROR: open brace '{' following function definitions go on the next line WARNING: printk() should include KERN_<LEVEL> facility level Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Bert Karwatzki <spasswolf@web.de> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Temporary Disable MST DP Colorspace PropertyFangzhi Zuo
Create MST colorsapce property for downstream device would trigger warning message "RIP: 0010:drm_mode_object_add+0x8e/0xa0 [drm]" After driver is loaded and drm device is registered, create dp colorspace property triggers warning storm at WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb); Temporary disabling MST dp colorspace property for now. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07Revert "drm/amdgpu: Prefer dev_* variant over printk in amdgpu_atpx_handler.c"Srinivasan Shanmugam
Usage of container_of is wrong here. struct acpi_device *adev = container_of(handle, struct acpi_device, handle) This reverts commit b0bd0a92b8158ea9c809d885e0f0c21518bdbd14. References: https://gitlab.freedesktop.org/drm/amd/-/issues/2744 Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Bert Karwatzki <spasswolf@web.de> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: check attr flag before set cursor degamma on DCN3+Melissa Wen
Don't set predefined degamma curve to cursor plane if the cursor attribute flag is not set. Applying a degamma curve to the cursor by default breaks userspace expectation. Checking the flag before performing any color transformation prevents too dark cursor gamma in DCN3+ on many Linux desktop environment (KDE Plasma, GNOME, wlroots-based, etc.) as reported at: - https://gitlab.freedesktop.org/drm/amd/-/issues/1513 This is the same approach followed by DCN2 drivers where the issue is not present. Fixes: 03f54d7d3448 ("drm/amd/display: Add DCN3 DPP") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1513 Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Clean up flip pending timeout handlingJoshua Aberback
[Why] Adjust timeout handling code for easier runtime manipulation during debug. Change has no functional effect by default. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: init TA microcode for SRIOV VF when MP0 IP is 13.0.6Zhigang Luo
Init TA ucode for SRIOV. Signed-off-by: Zhigang Luo <Zhigang.Luo@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amdgpu: remove SRIOV VF FB location programmingZhigang Luo
For SRIOV VF, FB location is programmed by host driver, no need to program it in guest driver. v2: squash in unused variable removal Signed-off-by: Zhigang Luo <Zhigang.Luo@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add Functions to enable Freesync Panel ReplayBhawanpreet Lakha
Add various functions for replay, such as construct, destroy, enable get_state, and copy_setting etc. These functions communicate with the firmware to setup and enable panel replay Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-05-29 21:58:57 +0000