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2021-02-09drm/amdkfd: Get unique_id dynamically v2Kent Russell
Instead of caching the value during amdgpu_device_init, just call the function directly. This avoids issues where the unique_id hasn't been saved by the time that KFD's topology snapshot is done (e.g. Arcturus). KFD's topology information from the amdgpu_device was initially cached at KFD initialization due to amdkfd and amdgpu being separate modules. Now that they are combined together, we can directly call the functions that we need and avoid this unnecessary duplication and complexity. As a side-effect of this change, we also remove unique_id=0 for CPUs, which is obviously not unique. v2: Drop previous patch printing unique_id in hex Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: enable ACDC featureKenneth Feng
The power limit and clock ragne are different in AC mode and DC mode. Firmware does the setting after this feature is enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu: enable gfx wave limiting for high priority compute jobsNirmoy Das
Enable gfx wave limiting for gfx jobs before pushing high priority compute jobs so that high priority compute jobs gets more resources to finish early. v2: use ring priority instead of job priority. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu: add wave limit functionality for gfx8,9Nirmoy Das
Wave limiting can be use to load balance high priority compute jobs along with gfx jobs. When enabled, this will reserve ~75% of waves for compute jobs. We do not need this from gfx10 onwards because >=gfx10 has asynchronous compute tunneling to replace wave limit requirement. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu: enable only one high prio compute queueNirmoy Das
For high priority compute to work properly we need to enable wave limiting on gfx pipe. Wave limiting is done through writing into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high priority compute queue to avoid race condition between multiple high priority compute queues writing that register simultaneously. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu: cleanup struct amdgpu_ringNirmoy Das
This patch consist of below related changes: 1 Rename ring->priority to ring->hw_prio. 2 Assign correct hardware ring priority. 3 Remove ring->priority_mutex as ring priority remains unchanged after initialization. 4 Remove unused ring->num_jobs. v3: remove ring->num_jobs. v2: remove ring->priority_mutex. Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/display: Fix unused variable warningBhawanpreet Lakha
[Why] The dm struct is only being used if DCN config is defined and this causes a unused variable warning if DCN option is not set. [How] Remove the compile flag so the variable is used (there also seems to be a duplicate guard due to a bad rebase) so remove the outer guard to fix the warning. Fixes this warning drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function 'dm_set_vblank': drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5380:33: warning: unused variable 'dm' [-Wunused-variable] Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09Revert "drm/amd/display: fix unused variable warning"Alex Deucher
This reverts commit 4c3a3292730c56591472717d8c5c0faf74f6c6bb. Bhawan's fix is better (less ifdefs), so revert this and apply Bhawan's. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-05drm/amd/display: fix unused variable warningArnd Bergmann
After all users of the 'dm' warnings got hidden in an #ifdef, the compiler started warning about it being unused: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable] Add another such #ifdef. Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org
2021-02-05Merge tag 'amd-drm-next-5.12-2021-02-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-02-03: amdgpu: - Display fixes and cleanups - Vangogh fixes - Fix possible race when there are timeouts on two rings - SR-IOV fixes - Add missing license - DCE 10/12 bpc fixes - Display MALL fixes - Fix SMU user preference settings persistence - Fix retry in gem allocate - Add new PCI DID - Fix for manual fan speed control on cards where it was problematic - Fix regression in pinning GTT - Misc display fixes - Misc code cleanups amdkfd: - Fix config handling - Fix regression in buffer free From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210204045717.3823-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
2021-02-05Merge tag 'mediatek-drm-next-5.12' of ↵Dave Airlie
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.12 1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210204151750.7550-1-chunkuang.hu@kernel.org
2021-02-04drm/mediatek: Add matrix_bits private data for ccorrYongqiang Niu
Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Fix ccorr size configYongqiang Niu
Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Separate ccorr moduleYongqiang Niu
ccorr ctm matrix bits will be different in mt8192. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Enable dither functionYongqiang Niu
Enable dither function to improve the display quality. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Enable OVL_LAYER_SMI_ID_EN for multi-layer usecaseYongqiang Niu
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add support for SoC MT8183Yongqiang Niu
1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add has_dither private data for gammaYongqiang Niu
Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Separate gamma moduleYongqiang Niu
mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add mtk_dither_set_common() functionHsin-Yi Wang
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04soc / drm: mediatek: Move mtk mutex driver to soc folderCK Hu
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-04drm/mediatek: Automatically search unclaimed mtk mutex in mtk_mutex_get()CK Hu
Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Change disp/ddp term to mutex in mtk mutex driverCK Hu
mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Rename file mtk_drm_ddp to mtk_mutexCK Hu
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Remove redundant file includingCK Hu
Those file includings are useless, so remove them. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add fifo_size into rdma private dataYongqiang Niu
Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Fix aal size configYongqiang Niu
The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d1392c26 ("drm/mediatek: Add AAL engine basic function") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: mtk_dpi: Create connector for bridgesHsin-Yi Wang
Similar to commit a9d9fea74be2 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Check if fb is nullYongqiang Niu
It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb980ec4 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04Merge tag 'drm-intel-next-2021-01-29' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129225328.GA1041349@intel.com
2021-02-04Merge tag 'drm/tegra/for-5.12-rc1' of ↵Dave Airlie
ssh://git.freedesktop.org/git/tegra/linux into drm-next drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129193807.3653456-1-thierry.reding@gmail.com
2021-02-02drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()Dan Carpenter
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02amd/display: remove unneeded variable: "pattern"Bernard Zhao
Remove unneeded variable: "pattern". Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: Disable GFXOFF when GFX DPM or PG disabledJinzhou Su
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: 3.2.121Aric Cyr
This version brings along following fixes: - Better handling of dummy p-state table - Workaround for some legacy DP-VGA dongles - Add Freesync HDMI support to DMCU - Enable "trigger_hotplug" debugfs on all outputs - fix initial bounding box values for dcn3.02 - implement support for DID2.0 dsc passthrough - fix calculation for the pwl backlight curve - Fix multiple memory leaks Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: [FW Promotion] Release 0.0.50Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Reject too small viewport size when validating planeNikola Cornij
[why] Overlay won't move to a new positon if viewport size is smaller than what can be handled. It'd either disappear or stay at the old position. This condition is for example hit if overlay is moved too much outside of left or top edge of the screen, but it applies to any non-cursor plane type. [how] Reject this contidion at validation time. This gives the calling level a chance to handle this gracefully and avoid inconsistent behaivor. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Better handling of dummy p-state tableJoshua Aberback
[Why] Some scenarios where we use a UCLK frequency in between dummy p-state table entries result in a p-state hang, due to the table not having a close enough match, so the default DPM0 latency is used, which can be too long to support dummy p-state switching in these scenarios. [How] - old: match if current freq is within +- margin of table entry - new: find largest table entry that is lower than current freq + margin - lower than DPM0 will still use DPM0 Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Workaround for some legacy DP-VGA donglesTaimur Hassan
[Why] Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and this leads to the maximum resolution 1920*1080 cannot be obtained from EDID. [How] Provide a workaround for some legacy DP-VGA dongles with a longer aux delay. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Decrement refcount of dc_sink before reassignmentVictor Lu
[why] An old dc_sink state is causing a memory leak because it is missing a dc_sink_release before a new dc_sink is assigned back to aconnector->dc_sink. [how] Decrement the dc_sink refcount before reassigning it to a new dc_sink. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Free atomic state after drm_atomic_commitVictor Lu
[why] drm_atomic_commit was changed so that the caller must free their drm_atomic_state reference on successes. [how] Add drm_atomic_commit_put after drm_atomic_commit call in dm_force_atomic_commit. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: remove unused force_ignore_link_settings debug optionWenjing Liu
[why] Remove force_ignore_link_settings debug option as it is no longer used. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add Freesync HDMI support to DMCUStylon Wang
[Why] Adding support for Freesync HDMI to DC and DMCU [How] Create DC interface and implementation on top of DMCU to support parsing CEA blocks in DMCU. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Enable "trigger_hotplug" debugfs on all outputsStylon Wang
[Why] Per-connector debugfs entry "trigger_hotplug" is available on DP/eDP only. New IGT tests need this entry to test other outputs. [How] Enable this debugfs entry on all types of connectors Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix CW4 programming for dmub30 cached inboxNicholas Kazlauskas
[Why] The conditions for whether we used cached vs non-cached inbox1 depend on a version check that mismatches what the shared helpers in dmub20 implement. [How] Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: fix initial bounding box values for dcn3.02Samson Tam
[Why] Initial bounding box values are updated in dcn30_update_bw_bounding_box but they use dcn3_0_soc and dcn3_0_ip instead of dcn3_02_soc and dcn3_02_ip [How] Add dcn302_update_bw_bounding_box and dcn302_get_optimal_dcfclk_fclk_for_uclk so it uses dcn3_02_soc and dcn3_02_ip. Use sr_exit_time_us, sr_enter_plus_exit_time_us, from dcn30 on dcn302 to fix flicker on eDP. Also use dram_clock_change_latency_us from dcn30. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: implement support for DID2.0 dsc passthroughJun Lei
[Why] Some panels contain active converters (e.g. DP to MIPI) which only support restricted DSC configurations. DID2.0 adds support for such displays to explicitly define per timing BPP restrictions on DSC. Ignoring these restrictions leads to blackscreen. [How] Add parsing in DID2.0 parser to get this bpp info. Add support in DSC module to constraint target bpp based on this info. Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix dc_sink kref count in emulated_link_detectVictor Lu
[why] prev_sink is not used anywhere else in the function and the reference to it from dc_link is replaced with a new dc_sink. [how] Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink). Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Release DSC before acquiringMikita Lipski
[why] Need to unassign DSC from pipes that are not using it so other pipes can acquire it. That is needed for asic's that have unmatching number of DSC engines from the number of pipes. [how] Before acquiring dsc to stream resources, first remove it. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Eryk Brol <Eryk.Brol@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Revert "Fix EDID parsing after resume from suspend"Stylon Wang
This reverts commit b24bdc37d03a0478189e20a50286092840f414fa. It caused memory leak after S3 on 4K HDMI displays. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-05-24 05:19:32 +0000