| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-11-07 | irqchip/exiu: Add support for Socionext Synquacer EXIU controller | Ard Biesheuvel | |
| The Socionext Synquacer SoC has an external interrupt unit (EXIU) that forwards a block of 32 configurable input lines to 32 adjacent level-high type GICv3 SPIs. The EXIU has per-interrupt level/edge and polarity controls, and mask bits that keep the outgoing lines de-asserted, even though the controller may still latch interrupt conditions that occur while the line is masked. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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