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path: root/drivers/irqchip
AgeCommit message (Expand)Author
2020-07-30irqchip/loongson-pch-pic: Fix the misused irq flow handlerHuacai Chen
2020-07-30irqchip/loongson-htvec: Support 8 groups of HT vectorsHuacai Chen
2020-07-30irqchip/loongson-liointc: Fix misuse of gc->mask_cacheHuacai Chen
2020-07-30irqchip/imx-intmux: Fix irqdata regs save in imx_intmux_runtime_suspend()Wei Yongjun
2020-07-27irqchip/imx-intmux: Implement intmux runtime power managementJoakim Zhang
2020-07-27irqchip/gic-v4.1: Use GFP_ATOMIC flag in allocate_vpe_l1_table()Zenghui Yu
2020-07-27irqchip/stm32-exti: Map direct event to irq parentAlexandre Torgue
2020-07-27irqchip/mtk-cirq: Convert to a platform driverSaravana Kannan
2020-07-27irqchip/mtk-sysirq: Convert to a platform driverSaravana Kannan
2020-07-27irqchip/qcom-pdc: Switch to using IRQCHIP_PLATFORM_DRIVER helper macrosSaravana Kannan
2020-07-27irqchip: Add IRQCHIP_PLATFORM_DRIVER_BEGIN/END and IRQCHIP_MATCH helper macrosSaravana Kannan
2020-07-27irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLRZenghui Yu
2020-07-27irqchip/irq-bcm7038-l1: Guard uses of cpu_logical_mapFlorian Fainelli
2020-07-27irqchip/qcom-pdc: Allow QCOM_PDC to be loadable as a permanent moduleJohn Stultz
2020-07-27irqchip/mips-gic: Make local symbols staticWei Yongjun
2020-07-27irqchip/ativic32: Constify irq_domain_opsMasahiro Yamada
2020-07-27irqchip/stm32-exti: Use the hwspin_lock_timeout_in_atomic() APIFabien Dessenne
2020-07-17irqchip/loongson-liointc: Fix potential dead lockTiezhu Yang
2020-07-17irqchip/loongson-pch-msi: Remove unneeded variableTiezhu Yang
2020-07-17irqchip/loongson-pch-pic: Check return value of irq_domain_translate_twocell()Tiezhu Yang
2020-07-17irqchip/loongson-htvec: Check return value of irq_domain_translate_onecell()Tiezhu Yang
2020-07-17irqchip/loongson-htvec: Fix potential resource leakTiezhu Yang
2020-07-17irqchip/loongson-htpic: Remove unneeded select of I8259Tiezhu Yang
2020-07-17irqchip/loongson-htpic: Remove redundant kfree operationTiezhu Yang
2020-07-17irqchip/irq-bcm7038-l1: Allow building on ARM 32-bitFlorian Fainelli
2020-07-17irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatibleFlorian Fainelli
2020-07-17irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatibleKamal Dasu
2020-07-17irqchip/brcmstb-l2: Set controller as wake-up sourceJustin Chen
2020-07-17irqchip/bcm7120-l2: Set controller as wake-up sourceJustin Chen
2020-06-27drivers/irqchip: Use new macro ACPI_DECLARE_SUBTABLE_PROBE_ENTRYOscar Carter
2020-06-27irqchip/atmel-aic5: Add support for sam9x60 rtt fixupClaudiu Beznea
2020-06-27irqchip/imx-intmux: Use struct_size() helper in devm_kzalloc()Gustavo A. R. Silva
2020-06-27irqchip/irq-mtk-sysirq: Replace spinlock with raw_spinlockBartosz Golaszewski
2020-06-27irqchip/vic: Cut down the external APILinus Walleij
2020-06-27irqchip/vic: Drop cascaded intialization callLinus Walleij
2020-06-27irqchip/ti-sci-inta: Fix typo about MODULE_AUTHORTiezhu Yang
2020-06-27irqchip/ti-sci-inta: Fix return value about devm_ioremap_resource()Tiezhu Yang
2020-06-27irqchip/ti-sci-inta: Remove dead code in ti_sci_inta_set_type()Tiezhu Yang
2020-06-09clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverAnup Patel
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel
2020-06-01irqchip: Fix "Loongson HyperTransport Vector support" driver build on all non...Ingo Molnar
2020-05-29irqchip: Add Loongson PCH MSI controllerJiaxun Yang
2020-05-29irqchip: Add Loongson PCH PIC controllerJiaxun Yang
2020-05-29irqchip: Add Loongson HyperTransport Vector supportJiaxun Yang
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel
2020-05-25irqchip/gic-v2, v3: Drop extra IRQ_NOAUTOEN setting for (E)PPIsValentin Schneider
2020-05-20irqchip/gic-v3-its: Balance initial LPI affinity across CPUsMarc Zyngier
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