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path: root/drivers/media/i2c/ccs-pll.c
AgeCommit message (Expand)Author
2021-02-01Merge tag 'v5.11-rc6' into patchworkMauro Carvalho Chehab
2021-01-12media: Revert "media: ccs-pll: Fix MODULE_LICENSE"Sakari Ailus
2021-01-12media: ccs-pll: Switch from standard integer types to kernel onesSakari Ailus
2021-01-07media: ccs-pll: Fix link frequency for C-PHYSakari Ailus
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus
2020-12-07media: ccs: Dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus
2020-12-03media: ccs: Change my e-mail addressSakari Ailus
2020-12-03media: ccs-pll: Fix MODULE_LICENSESakari Ailus
2020-12-03media: smiapp-pll: Rename as ccs-pllSakari Ailus
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