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path: root/drivers/memory/mtk-smi.c
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2019-10-15memory: mtk-smi: Add PM suspend and resume opsYong Wu
In the commit 4f0a1a1ae351 ("memory: mtk-smi: Invoke pm runtime_callback to enable clocks"), we use pm_runtime callback to enable/disable the smi larb clocks. It will cause the larb's clock may not be disabled when suspend. That is because device_prepare will call pm_runtime_get_noresume which will keep the larb's PM runtime status still is active when suspend, then it won't enter our pm_runtime suspend callback to disable the corresponding clocks. This patch adds suspend pm_ops to force disable the clocks, Use "LATE" to make sure it disable the larb's clocks after the multimedia devices. Fixes: 4f0a1a1ae351 ("memory: mtk-smi: Invoke pm runtime_callback to enable clocks") Signed-off-by: Anan Sun <anan.sun@mediatek.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30iommu/mediatek: Clean up struct mtk_smi_iommuYong Wu
Remove the "struct mtk_smi_iommu" to simplify the code since it has only one item in it right now. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Get rid of need_larbidYong Wu
The "mediatek,larb-id" has already been parsed in MTK IOMMU driver. It's no need to parse it again in SMI driver. Only clean some codes. This patch is fit for all the current mt2701, mt2712, mt7623, mt8173 and mt8183. After this patch, the "mediatek,larb-id" only be needed for mt2712 which have 2 M4Us. In the other SoCs, we can get the larb-id from M4U in which the larbs in the "mediatek,larbs" always are ordered. Correspondingly, the larb_nr in the "struct mtk_smi_iommu" could also be deleted. CC: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Add bus_sel for mt8183Yong Wu
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering mmu0 or mmu1 to balance the bandwidth via the smi-common register SMI_BUS_SEL(0x220)(Each larb occupy 2 bits). In mt8183, For better performance, we switch larb1/2/5/7 to enter mmu1 while the others still keep enter mmu0. In mt8173 and mt2712, we don't get the performance issue, Keep its default value(0x0), that means all the larbs enter mmu0. Note: smi gen1(mt2701/mt7623) don't have this bus_sel. And, the base of smi-common is completely different with smi_ao_base of gen1, thus I add new variable for that. CC: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Invoke pm runtime_callback to enable clocksYong Wu
This patch only move the clk_prepare_enable and config_port into the runtime suspend/resume callback. It doesn't change the code content and sequence. This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. (SMI_BUS_SEL need to be restored after smi-common resume every time.) Also it gives a chance to get rid of mtk_smi_larb_get/put which could be a next topic. CC: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30iommu/mediatek: Add mt8183 IOMMU supportYong Wu
The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. Here list main differences between mt8183 and mt8173/mt2712: 1) mt8183 has only one M4U HW like mt8173 while mt2712 has two. 2) mt8183 don't have the "bclk" clock, it use the EMI clock instead. 3) mt8183 can support the dram over 4GB, but it doesn't call this "4GB mode". 4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent the bit[33:32] in the physical address of the pgtable base, But the standard ttbr0[1] means the S bit which is enabled defaultly, Hence, we add a mask. 5) mt8183 HW has a GALS modules, SMI should enable "has_gals" support. 6) mt8183 need reset_axi like mt8173. 7) the larb-id in smi-common is remapped. M4U should add its larbid_remap. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Add gals supportYong Wu
In some SoCs like mt8183, SMI add GALS(Global Async Local Sync) module which can help synchronize for the modules in different clock frequency. It can be seen as a "asynchronous fifo". This is a example diagram: M4U | ---------- | | gals0-rx gals1-rx | | | | gals0-tx gals1-tx | | ------------ SMI Common ------------ | +-----+--------+-----+- ... | | | | | gals-rx gals-rx | | | | | | | | | | gals-tx gals-tx | | | | | larb1 larb2 larb3 larb4 GALS only help transfer the command/data while it doesn't have the configuring register, thus it has the special "smi" clock and doesn't have the "apb" clock. From the diagram above, we add "gals0" and "gals1" clocks for smi-common and add a "gals" clock for smi-larb. This patch adds gals clock supporting in the SMI. Note that some larbs may still don't have the "gals" clock like larb1 and larb4 above. This is also a preparing patch for mt8183 which has GALS. CC: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Use a struct for the platform data for smi-commonYong Wu
Use a struct as the platform special data instead of the enumeration. Also there is a minor change that moving the position of "enum mtk_smi_gen" definition, this is because we expect define "struct mtk_smi_common_plat" before it is referred. This is a preparing patch for mt8183. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-08-30memory: mtk-smi: Use a general config_port interfaceYong Wu
The config_port of mt2712 and mt8183 are the same. Use a general config_port interface instead. In addition, in mt2712, larb8 and larb9 are the bdpsys larbs which are not the normal larb, their register space are different from the normal one. thus, we can not call the general config_port. In mt8183, IPU0/1 and CCU connect with smi-common directly, they also are not the normal larb. Hence, we add a "larb_direct_to_common_mask" for these larbs which connect to smi-commmon directly. This is also a preparing patch for adding mt8183 SMI support. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-08-22memory: mtk-smi: Degrade SMI init to module_initYong Wu
The initialization of MediaTek power manager(SCPSYS) is builtin_platform_driver, and SMI must depend on power-domain. Thus, currently subsys_initcall for SMI is unnecessary, SMI will be always probe defered by power-domain. Degrade it to module_init. In addition, there are two small changes about the probe sequence: 1) Delete this two lines. if (!dev->pm_domain) return -EPROBE_DEFER; This is not helpful. the platform driver framework guarantee this. The "dev_pm_domain_attach" in the "platform_drv_probe" will return EPROBE_DEFER if its powerdomain is not ready. 2) Add the probe-defer for the smi-larb device should waiting for smi-common. In mt2712, there are 2 smi-commons, 10 smi-larbs. All will be probe-defered by the power-domain, there is seldom case that smi-larb probe done before smi-common. then it will hang like this: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = ffffff800a4e0000 [00000000] *pgd=00000000beffe003[ 17.610026] , *pud=00000000beffe003 ... [<ffffff800897fe04>] mtk_smi_enable+0x1c/0xd0 [<ffffff800897fee8>] mtk_smi_larb_get+0x30/0x98 [<ffffff80088edfa8>] mtk_mipicsi0_resume+0x38/0x1b8 [<ffffff8008634f44>] pm_generic_runtime_resume+0x3c/0x58 [<ffffff8008644ff8>] __genpd_runtime_resume+0x38/0x98 [<ffffff8008647434>] genpd_runtime_resume+0x164/0x220 [<ffffff80086372f8>] __rpm_callback+0x78/0xa0 [<ffffff8008637358>] rpm_callback+0x38/0xa0 [<ffffff8008638a4c>] rpm_resume+0x4a4/0x6f8 [<ffffff8008638d04>] __pm_runtime_resume+0x64/0xa0 [<ffffff80088ed05c>] mtk_mipicsi0_probe+0x40c/0xb70 [<ffffff800862cdc0>] platform_drv_probe+0x58/0xc0 [<ffffff800862a514>] driver_probe_device+0x284/0x438 [<ffffff800862a8ac>] __device_attach_driver+0xb4/0x160 [<ffffff8008627d58>] bus_for_each_drv+0x68/0xa8 [<ffffff800862a0a4>] __device_attach+0xd4/0x168 [<ffffff800862a9d4>] device_initial_probe+0x24/0x30 [<ffffff80086291d8>] bus_probe_device+0xa0/0xa8 [<ffffff8008629784>] deferred_probe_work_func+0x94/0xf0 [<ffffff80080f03a8>] process_one_work+0x1d8/0x6e0 Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-08-22iommu/mediatek: Add mt2712 IOMMU supportYong Wu
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-08-15memory: mtk-smi: Handle return value of clk_prepare_enableArvind Yadav
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-08-04memory: mtk-smi: add larbid handle routineHonghui Zhang
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"), the larb->larbid was added but not initialized. Mediatek's gen1 smi need this hardware larbid information to get the register offset which controls whether enable iommu for this larb. This patch add the initialize routine for larbid. Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-08-04memory: mtk-smi: Use of_device_get_match_data helperHonghui Zhang
Replace custom code with generic helper to retrieve driver data. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-06-21memory/mediatek: add support for mt2701Honghui Zhang
Mediatek SMI has two generations of HW architecture, mt8173 uses the second generation of SMI HW while mt2701 uses the first generation HW of SMI. There's slight differences between the two generations, for generation 2, the register which control the iommu port access PA or IOVA is at each larb's register base. But for generation 1, the register is at smi ao base(smi always on register base). Besides that, the smi async clock should be prepared and enabled for SMI generation 1 HW to transform the smi clock into emi clock domain, but is not needed for SMI generation 2. This patch add SMI driver for mt2701 which use generation 1 SMI HW. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-05-06memory: mtk-smi: export mtk_smi_larb_get/putPhilipp Zabel
To allow building mediatek-drm.ko as a module, the mtk_smi_larb_get and mtk_smi_larb_put symbols have to be exported. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-02-25memory: mediatek: Add SMI driverYong Wu
This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>