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2023-03-13memory: tegra30-emc: fix interconnect registration raceJohan Hovold
The current interconnect provider registration interface is inherently racy as nodes are not added until the after adding the provider. This can specifically cause racing DT lookups to fail. Switch to using the new API where the provider is not registered until after it has been fully initialised. Fixes: d5ef16ba5fbe ("memory: tegra20: Support interconnect framework") Cc: stable@vger.kernel.org # 5.11 Cc: Dmitry Osipenko <digetx@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230306075651.2449-21-johan+linaro@kernel.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-03-13memory: tegra20-emc: fix interconnect registration raceJohan Hovold
The current interconnect provider registration interface is inherently racy as nodes are not added until the after adding the provider. This can specifically cause racing DT lookups to fail. Switch to using the new API where the provider is not registered until after it has been fully initialised. Fixes: d5ef16ba5fbe ("memory: tegra20: Support interconnect framework") Cc: stable@vger.kernel.org # 5.11 Cc: Dmitry Osipenko <digetx@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230306075651.2449-20-johan+linaro@kernel.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-03-13memory: tegra124-emc: fix interconnect registration raceJohan Hovold
The current interconnect provider registration interface is inherently racy as nodes are not added until the after adding the provider. This can specifically cause racing DT lookups to fail. Switch to using the new API where the provider is not registered until after it has been fully initialised. Fixes: 380def2d4cf2 ("memory: tegra124: Support interconnect framework") Cc: stable@vger.kernel.org # 5.12 Cc: Dmitry Osipenko <digetx@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230306075651.2449-19-johan+linaro@kernel.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-03-13memory: tegra: fix interconnect registration raceJohan Hovold
The current interconnect provider registration interface is inherently racy as nodes are not added until the after adding the provider. This can specifically cause racing DT lookups to fail. Switch to using the new API where the provider is not registered until after it has been fully initialised. Fixes: 06f079816d4c ("memory: tegra-mc: Add interconnect framework") Cc: stable@vger.kernel.org # 5.11 Cc: Dmitry Osipenko <digetx@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230306075651.2449-18-johan+linaro@kernel.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-03-09memory: tegra: remove MODULE_LICENSE in non-modulesNick Alcock
Since commit 8b41fc4454e3 ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230308202117.426808-1-nick.alcock@oracle.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-12-27memory: tegra: Remove clients SID override programmingAshish Mhetre
On newer Tegra releases, early boot SID override programming and SID override programming during resume is handled by bootloader. In the function tegra186_mc_program_sid() which is getting removed, SID override register of all clients is written without checking if secure firmware has allowed write on it or not. If write is disabled by secure firmware then it can lead to errors coming from secure firmware and hang in kernel boot. Also, SID override is programmed on-demand during probe_finalize() call of IOMMU which is done in tegra186_mc_client_sid_override() in this same file. This function does it correctly by checking if write is permitted on SID override register. It also checks if SID override register is already written with correct value and skips re-writing it in that case. Fixes: 393d66fd2cac ("memory: tegra: Implement SID override programming") Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221125040752.12627-1-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-12-13Merge tag 'drm-next-2022-12-13' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm updates from Dave Airlie: "The biggest highlight is that the accel subsystem framework is merged. Hopefully for 6.3 we will be able to line up a driver to use it. In drivers land, i915 enables DG2 support by default now, and nouveau has a big stability refactoring and initial ampere support, AMD includes new hw IP support and should build on ARM again. There is also an ofdrm driver to take over offb on platforms it's used. Stuff outside my tree, the dma-buf patches hit a few places, the vc4 firmware changes also do, and i915 has some interactions with MEI for discrete GPUs. I think all of those should have been acked/reviewed by relevant parties. New driver: - ofdrm - replacement for offb fbdev: - add support for nomodeset fourcc: - add Vivante tiled modifier core: - atomic-helpers: CRTC primary plane test fixes, fb access hooks - connector: TV API consistency, cmdline parser improvements - send connector hotplug on cleanup - sort makefile objects tests: - sort kunit tests - improve DP-MST tests - add kunit helpers to create a device sched: - module param for scheduling policy - refcounting fix buddy: - add back random seed log ttm: - convert ttm_resource to size_t - optimize pool allocations edid: - HFVSDB parsing support fixes - logging/debug improvements - DSC quirks dma-buf: - Add unlocked vmap and attachment mapping - move drivers to common locking convention - locking improvements firmware: - new API for rPI firmware and vc4 xilinx: - zynqmp: displayport bridge support - dpsub fix bridge: - adv7533: Remove dynamic lane switching - it6505: Runtime PM support, sync improvements - ps8640: Handle AUX defer messages - tc358775: Drop soft-reset over I2C panel: - panel-edp: Add INX N116BGE-EA2 C2 and C4 support. - Jadard JD9365DA-H3 - NewVision NV3051D amdgpu: - DCN support on ARM - DCN 2.1 secure display - Sienna Cichlid mode2 reset fixes - new GC 11.x firmware versions - drop AMD specific DSC workarounds in favour of drm code - clang warning fixes - scheduler rework - SR-IOV fixes - GPUVM locking fixes - fix memory leak in CS IOCTL error path - flexible array updates - enable new GC/PSP/SMU/NBIO IP - GFX preemption support for gfx9 amdkfd: - cache size fixes - userptr fixes - enable cooperative launch on gfx 10.3 - enable GC 11.0.4 KFD support radeon: - replace kmap with kmap_local_page - ACPI ref count fix - HDA audio notifier support i915: - DG2 enabled by default - MTL enablement work - hotplug refactoring - VBT improvements - Display and watermark refactoring - ADL-P workaround - temp disable runtime_pm for discrete- - fix for A380 as a secondary GPU - Wa_18017747507 for DG2 - CS timestamp support fixes for gen5 and earlier - never purge busy TTM objects - use i915_sg_dma_sizes for all backends - demote GuC kernel contexts to normal priority - gvt: refactor for new MDEV interface - enable DC power states on eDP ports - fix gen 2/3 workarounds nouveau: - fix page fault handling - Ampere acceleration support - driver stability improvements - nva3 backlight support msm: - MSM_INFO_GET_FLAGS support - DPU: XR30 and P010 image formats - Qualcomm SM6115 support - DSI PHY support for QCM2290 - HDMI: refactored dev init path - remove exclusive-fence hack - fix speed-bin detection - enable clamp to idle on 7c3 - improved hangcheck detection vmwgfx: - fb and cursor refactoring - convert to generic hashtable - cursor improvements etnaviv: - hw workarounds - softpin MMU fixes ast: - atomic gamma LUT support - convert to SHMEM lcdif: - support YUV planes - Increase DMA burst size - FIFO threshold tuning meson: - fix return type of cvbs mode_valid mgag200: - fix PLL setup on some revisions sun4i: - A100 and D1 support udl: - modesetting improvements - hot unplug support vc4: - support PAL-M - fix regression preventing 4K @ 60Hz - fix NULL ptr deref v3d: - switch to drm managed resources renesas: - RZ/G2L DSI support - DU Kconfig cleanup mediatek: - fixup dpi and hdmi - MT8188 dpi support - MT8195 AFBC support tegra: - NVDEC hardware on Tegra234 SoC hdlcd: - switch to drm managed resources ingenic: - fix registration error path hisilicon: - convert to drm_mode_init maildp: - use managed resources mtk: - use drm_mode_init rockchip: - use drm_mode_copy" * tag 'drm-next-2022-12-13' of git://anongit.freedesktop.org/drm/drm: (1397 commits) drm/amdgpu: fix mmhub register base coding error drm/amdgpu: add tmz support for GC IP v11.0.4 drm/amdgpu: enable GFX Clock Gating control for GC IP v11.0.4 drm/amdgpu: enable GFX Power Gating for GC IP v11.0.4 drm/amdgpu: enable GFX IP v11.0.4 CG support drm/amdgpu: Make amdgpu_ring_mux functions as static drm/amdgpu: generally allow over-commit during BO allocation drm/amd/display: fix array index out of bound error in DCN32 DML drm/amd/display: 3.2.215 drm/amd/display: set optimized required for comp buf changes drm/amd/display: Add debug option to skip PSR CRTC disable drm/amd/display: correct DML calc error of UrgentLatency drm/amd/display: correct static_screen_event_mask drm/amd/display: Ensure commit_streams returns the DC return code drm/amd/display: read invalid ddc pin status cause engine busy drm/amd/display: Bypass DET swath fill check for max clocks drm/amd/display: Disable uclk pstate for subvp pipes drm/amd/display: Fix DCN2.1 default DSC clocks drm/amd/display: Enable dp_hdmi21_pcon support drm/amd/display: prevent seamless boot on displays that don't have the preferred dig ...
2022-11-25memory: tegra: Add API for retrieving carveout boundsMikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it has been loaded by a bootloader. When booting NVDEC, we need to tell it the address of this firmware, which we can determine by checking the starting address of the carveout. As such, add an MC API to query the bounds of carveouts, and add related information on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21memory: tegra: Add DLA clients for Tegra234Jon Hunter
Add the memory clients on Tegra234 which are needed for initialising the SMMU for the Deep Learning Accelerator (DLA). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21memory: tegra186-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify codeLiu Shixin
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21memory: tegra210-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify codeLiu Shixin
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21memory: tegra30-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify codeLiu Shixin
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21memory: tegra20-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify codeLiu Shixin
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-08-03Merge tag 'opp-updates-5.20-rc1' of ↵Rafael J. Wysocki
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Pull operating performance points (OPP) updates for 5.20-rc1 from Viresh Kumar: "- Make dev_pm_opp_set_regulators() accept NULL terminated list (Viresh Kumar). - Add dev_pm_opp_set_config() and friends and migrate other users/helpers to using them (Viresh Kumar). - Add support for multiple clocks for a device (Viresh Kumar and Krzysztof Kozlowski). - Configure resources before adding OPP table for Venus (Stanimir Varbanov). - Keep reference count up for opp->np and opp_table->np while they are still in use (Liang He). - Minor cleanups (Viresh Kumar and Yang Li)." * tag 'opp-updates-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: (43 commits) venus: pm_helpers: Fix warning in OPP during probe OPP: Don't drop opp->np reference while it is still in use OPP: Don't drop opp_table->np reference while it is still in use OPP: Remove dev{m}_pm_opp_of_add_table_noclk() PM / devfreq: tegra30: Register config_clks helper OPP: Allow config_clks helper for single clk case OPP: Provide a simple implementation to configure multiple clocks OPP: Assert clk_count == 1 for single clk helpers OPP: Add key specific assert() method to key finding helpers OPP: Compare bandwidths for all paths in _opp_compare_key() OPP: Allow multiple clocks for a device dt-bindings: opp: accept array of frequencies OPP: Make dev_pm_opp_set_opp() independent of frequency OPP: Reuse _opp_compare_key() in _opp_add_static_v2() OPP: Remove rate_not_available parameter to _opp_add() OPP: Use consistent names for OPP table instances OPP: Use generic key finding helpers for bandwidth key OPP: Use generic key finding helpers for level key OPP: Add generic key finding helpers and use them for freq APIs OPP: Remove dev_pm_opp_find_freq_ceil_by_volt() ...
2022-07-08memory: tegra: Add MGBE memory clients for Tegra234Thierry Reding
Tegra234 has multiple network interfaces with each their own memory clients and stream IDs to allow for proper isolation. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08OPP: Migrate set-supported-hw API to use set-config helpersViresh Kumar
Now that we have a central API to handle all OPP table configurations, migrate the set-supported-hw family of helpers to use the new infrastructure. The return type and parameter to the APIs change a bit due to this, update the current users as well in the same commit in order to avoid breaking builds. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-05-09Merge tag 'memory-controller-drv-tegra-5.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.19 - Tegra SoC Add support for Tegra234 memory controller and for logging memory controller errors on Tegra186, Tegra194 and Tegra234. * tag 'memory-controller-drv-tegra-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra: Add MC error logging on Tegra186 onward memory: tegra: Add memory controller channels support memory: tegra: Add APE memory clients for Tegra234 memory: tegra: Add Tegra234 support Link: https://lore.kernel.org/r/20220509160807.154187-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-09memory: tegra: Add MC error logging on Tegra186 onwardAshish Mhetre
Add support for logging memory controller errors on Tegra186, Tegra194 and Tegra234. On these SoCs, interrupts can occur on multiple channels. Add support required to read the status of interrupts across multiple channels, log and clear them. Also add new interrupts supported on these SoCs. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-5-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-09memory: tegra: Add memory controller channels supportAshish Mhetre
From Tegra186 onwards, the memory controller supports multiple channels. Add support for mapping the address spaces of these channels and specify the number of channels supported by Tegra186, Tegra194 and Tegra234. In case of old bindings, channels won't be present. If channels are not present then print a warning and continue so that backward compatibility will be preserved in driver. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-4-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-09memory: tegra: Add APE memory clients for Tegra234Sameer Pujar
Add the memory clients on Tegra234 which are needed for APE DMA to properly use the SMMU. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-3-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-09memory: tegra: Add Tegra234 supportThierry Reding
The memory controller and external memory controller found on Tegra234 is similar to the version found on earlier SoCs but supports a number of new memory clients. Add initial memory client definitions for the Tegra234 so that the SMMU stream ID override registers can be properly programmed at boot time. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-26memory: tegra: mc: simplify platform_get_resource()Krzysztof Kozlowski
Use devm_platform_ioremap_resource() instead of platform_get_resource() and devm_ioremap_resource(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220419142859.380566-5-krzysztof.kozlowski@linaro.org
2022-01-27memory: tegra: Constify struct thermal_cooling_device_opsRikard Falkeborn
The only usage of tegra210_emc_cd_ops is to pass its address to devm_thermal_of_cooling_device_register() which is a pointer to const struct thermal_cooling_device_ops. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20211128204158.19544-1-rikard.falkeborn@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-27memory: tegra20-emc: Correct memory device maskDmitry Osipenko
Memory chip select is swapped when we read mode register, correct it. We didn't have devices that use a single LPDDR chip and both chips are always identical, hence this change is just a minor improvement. Fixes: 131dd9a436d8 ("memory: tegra20-emc: Support matching timings by LPDDR2 configuration") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211222043215.28237-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-27memory: tegra30-emc: Print additional memory infoDmitry Osipenko
Print out memory type and LPDDR2 configuration on Tegra30, making it similar to the memory info printed by the Tegra20 memory driver. This info is useful for debugging purposes. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # T30 ASUS TF201 LPDDR2 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211222043215.28237-1-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-21Merge tag 'memory-controller-drv-5.16-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.16, part two 1. Convert LPDDR2 bindings to dtschema and extend them with new properties. 2. Tegra 20 EMC: support matching timings by LPDDR2 configuration from devicetree. * tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra20-emc: Add runtime dependency on devfreq governor module memory: tegra20-emc: Support matching timings by LPDDR2 configuration memory: Add LPDDR2-info helpers dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node dt-bindings: Add vendor prefix for Elpida Memory dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F dt-bindings: memory: lpddr2: Add revision-id properties dt-bindings: memory: lpddr2: Convert to schema dt-bindings: Relocate DDR bindings Link: https://lore.kernel.org/r/20211021093002.118192-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21memory: tegra20-emc: Add runtime dependency on devfreq governor moduleDmitry Osipenko
Tegra20 EMC driver uses simple devfreq governor. Add simple devfreq governor to the list of the Tegra20 EMC driver module softdeps to allow userspace initramfs tools like dracut to automatically pull the devfreq module into ramfs image together with the EMC module. Reported-by: Nicolas Chauvet <kwizart@gmail.com> Suggested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211019231524.888-1-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-15memory: tegra20-emc: Support matching timings by LPDDR2 configurationDmitry Osipenko
ASUS Transformer TF101 doesn't provide RAM code and in this case memory timings should be selected based on identity information read out from SDRAM chip. Support matching timings by LPDDR2 configuration. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-07memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE withKai Song
fix debugfs_simple_attr.cocci warning: drivers/memory/tegra/tegra210-emc-core.c:1665:0-23: WARNING:tegra210_emc_debug_min_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE Commit 6fc5f1adf5a1 ("memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE") fixed the same warning, but didn't fix all matches in this file at once. Signed-off-by: Kai Song <songkai01@inspur.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20211005043514.9650-1-songkai01@inspur.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-07memory: tegra186-emc: Fix error return code in tegra186_emc_probe()Yang Yingliang
Return the error code when command fails. Fixes: 13324edbe926 ("memory: tegra186-emc: Handle errors in BPMP response") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20210928021545.3774677-1-yangyingliang@huawei.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-24memory: tegra: Make use of the helper function devm_add_action_or_reset()Cai Huoqing
Use devm_add_action_or_reset() instead of devm_add_action() to simplify the error handling. Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210922130002.586-1-caihuoqing@baidu.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-20memory: tegra186-emc: Handle errors in BPMP responseMikko Perttunen
The return value from tegra_bpmp_transfer indicates the success or failure of the IPC transaction with BPMP. If the transaction succeeded, we also need to check the actual command's result code. Add code to do this. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20210915085517.1669675-3-mperttunen@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-20memory: tegra: Remove interconnect state syncing hackDmitry Osipenko
State syncing works properly now, previously the sync callback was never invoked. Apparently it was fixed in drivers core, so let's remove the hack. The state won't be synced until all consumer drivers of devices that reference memory controller in a device-tree are probed, i.e. keeping bandwidth at maximum until both display and devfreq drivers are probed. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20210912183009.6400-1-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with ↵Jing Yangyang
DEFINE_DEBUGFS_ATTRIBUTE Fix the following coccicheck warning: drivers/memory/tegra/tegra210-emc-core.c:1665:0-23:WARNING tegra210_emc_debug_min_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE Signed-off-by: Jing Yangyang <jing.yangyang@zte.com.cn> Link: https://lore.kernel.org/r/20210825063739.70260-1-deng.changcheng@zte.com.cn Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15memory: tegra30-emc: replace DEFINE_SIMPLE_ATTRIBUTE with ↵jing yangyang
DEFINE_DEBUGFS_ATTRIBUTE Fix the following coccicheck warning: drivers/memory/tegra/tegra30-emc.c:1322:0-23:WARNING: tegra_emc_debug_max_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE Signed-off-by: jing yangyang <jing.yangyang@zte.com.cn> Link: https://lore.kernel.org/r/20210821035223.28282-1-jing.yangyang@zte.com.cn Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15memory: tegra: make the array list static const, makes object smallerColin Ian King
Don't populate the array list on the stack but instead it static const. Makes the object code smaller by 110 bytes: Before: text data bss dec hex filename 37713 21992 64 59769 e979 .../tegra/tegra210-emc-cc-r21021.o After: text data bss dec hex filename 37539 22056 64 59659 e90b .../tegra/tegra210-emc-cc-r21021.o (gcc version 10.3.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210819133155.10441-1-colin.king@canonical.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-07-23memory: tegra: fix unused-function warningArnd Bergmann
The tegra186_mc_client_sid_override() is only called from an #ifdef block: drivers/memory/tegra/tegra186.c:74:13: error: 'tegra186_mc_client_sid_override' defined but not used [-Werror=unused-function] 74 | static void tegra186_mc_client_sid_override(struct tegra_mc *mc, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Add another #ifdef around the called function. Fixes: 393d66fd2cac ("memory: tegra: Implement SID override programming") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20210722090748.1157470-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: tegra: Delete dead debugfs checking codeDan Carpenter
The debugfs_create_dir() function does not return NULL, it returns error pointers. But in normal situations like this where the caller is not dereferencing "emc->debugfs.root" then we are not supposed to check the return. So instead of fixing these checks, we should delete them. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YMCQDTSyG8UuQoh0@mwanda Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Implement SID override programmingThierry Reding
Instead of programming all SID overrides during early boot, perform the operation on-demand after the SMMU translations have been set up for a device. This reuses data from device tree to match memory clients for a device and programs the SID specified in device tree, which corresponds to the SID used for the SMMU context banks for the device. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210603164632.1000458-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Split Tegra194 data into separate fileThierry Reding
Keep the directory structure consistent by splitting the Tegra194 data into a separate file. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-13-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Add memory client IDs to tablesThierry Reding
The memory client IDs will subsequently be used to program override SIDs for the given clients depending on the device tree configuration. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-12-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Unify driversThierry Reding
The Tegra210 (and earlier) driver now supports all the functionality that the Tegra186 (and later) driver does, so they can be unified. Note that previously the Tegra186 (and later) driver could be unloaded, even if that was perhaps not very useful. Older chips don't support that yet, but once they do this code can be reenabled. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-11-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Only initialize reset controller if availableThierry Reding
The memory controller hot resets are implemented in the BPMP on Tegra186 and later, so there's no need to provide an implementation via the memory controller driver. Conditionally register the reset controller only if needed. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-10-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Make IRQ support opitonalThierry Reding
Make IRQ support optional to help unify the Tegra186 memory controller driver with this one. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-9-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Parameterize interrupt handlerThierry Reding
Tegra20 requires a slightly different interrupt handler than Tegra30 and later, so parameterize the handler, so that each SoC implementation can provide its own. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-8-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Extract setup code into callbackThierry Reding
Separate the setup code for Tegra30 and later into a ->setup() callback and set it for all applicable chips. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-7-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Make per-SoC setup more genericThierry Reding
The current per-SoC setup code runs at a fairly arbitrary point during probe, thereby making it less flexible for other SoC generations. Move the call around slightly (after only the very basic, common setup that applies to all SoC generations has been performed), which will allow it to be used for other implementations. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-6-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Push suspend/resume into SoC driversThierry Reding
Continuing the scheme of unification, push suspend/resume callbacks into per-SoC driver so that they can be properly parameterized. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-5-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Introduce struct tegra_mc_opsThierry Reding
Subsequent patches will introduce further callbacks, so create a new struct tegra_mc_ops to collect all of them in a single place. Move the existing ->init() callback into the new structure. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-4-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra: Unify struct tegra_mc across SoC generationsThierry Reding
As another step towards unifying both the Tegra210 (and earlier) and Tegra186 (and later) memory controller drivers, unify the structures that are used to represent them. Note that this comes at a slight space penalty since some fields are not used on all generations, but the benefits of unifying the driver outweigh the downsides. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-3-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
generated by cgit (git 2.34.1) at 2025-07-24 09:11:29 +0000