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path: root/drivers/mmc/host/sdhci.c
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2020-01-24mmc: sdhci: Let a vendor driver supply and update ADMA descriptor sizeVeerabhadrarao Badiganti
Let a vendor driver supply the maximum descriptor size that it can operate on. ADMA descriptor table would be allocated using this supplied size. If any SD Host controller is of version prior to v4.10 spec but supports 16byte descriptor, this change allows them to supply correct descriptor size for ADMA table allocation. Also let a vendor driver update the descriptor size by overriding sdhc_host->desc_size if it has to operates on a different descriptor sizes in different conditions. Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579531122-28341-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20mmc: sdhci: fix an issue of mixing different typesChunyan Zhang
Fix an issue reported by sparse, since mixed types of parameters are used on calling dmaengine_prep_slave_sg(). Fixes: 36e1da441fec (mmc: sdhci: add support for using external DMA devices) Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200120033223.897-1-zhang.chunyan@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20Merge branch 'fixes' into nextUlf Hansson
2020-01-20mmc: sdhci: fix minimum clock rate for v3 controllerMichał Mirosław
For SDHCIv3+ with programmable clock mode, minimal clock frequency is still base clock / max(divider). Minimal programmable clock frequency is always greater than minimal divided clock frequency. Without this patch, SDHCI uses out-of-spec initial frequency when multiplier is big enough: mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz [for 480 MHz source clock divided by 1024] The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode. Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode") Cc: <stable@vger.kernel.org> # 4f6aa3264af4: mmc: tegra: Only advertise UHS modes if IO regulator is present Cc: <stable@vger.kernel.org> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20mmc: sdhci: Refactor sdhci_set_timeout()Faiz Abbas
Refactor sdhci_set_timeout() such that platform drivers can do some functionality in a set_timeout() callback and then call __sdhci_set_timeout() to complete the operation. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20mmc: sdhci: Convert sdhci_set_timeout_irq() to non-staticFaiz Abbas
Export sdhci_set_timeout_irq() so that it is accessible from platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20mmc: sdhci: add support for using external DMA devicesChunyan Zhang
Some standard SD host controllers can support both external dma controllers as well as ADMA/SDMA in which the SD host controller acts as DMA master. TI's omap controller is the case as an example. Currently the generic SDHCI code supports ADMA/SDMA integrated in the host controller but does not have any support for external DMA controllers implemented using dmaengine, meaning that custom code is needed for any systems that use an external DMA controller with SDHCI. Fixes by Faiz Abbas <faiz_abbas@ti.com>: 1. Map scatterlists before dmaengine_prep_slave_sg() 2. Use dma_async() functions inside of the send_command() path and call terminate_sync() in non-atomic context in case of an error. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-20mmc: sdhci: Factor out some operations set to their own functionsFaiz Abbas
In preparation for adding external dma support, factor out data initialization, block info and mrq_done to their own functions. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Tested-by: Baolin Wang <baolin.wang7@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200116105154.7685-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18Merge branch 'fixes' into nextUlf Hansson
2019-12-18mmc: sdhci: Add a quirk for broken command queuingAdrian Hunter
Command queuing has been reported broken on some systems based on Intel GLK. A separate patch disables command queuing in some cases. This patch adds a quirk for broken command queuing, which enables users with problems to disable command queuing using sdhci module parameters for quirks. Fixes: 8ee82bda230f ("mmc: sdhci-pci: Add CQHCI support for Intel GLK") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191217095349.14592-2-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16Merge branch 'fixes' into nextUlf Hansson
2019-12-16mmc: sdhci: Update the tuning failed messages to pr_debug levelFaiz Abbas
Tuning support in DDR50 speed mode was added in SD Specifications Part1 Physical Layer Specification v3.01. Its not possible to distinguish between v3.00 and v3.01 from the SCR and that is why since commit 4324f6de6d2e ("mmc: core: enable CMD19 tuning for DDR50 mode") tuning failures are ignored in DDR50 speed mode. Cards compatible with v3.00 don't respond to CMD19 in DDR50 and this error gets printed during enumeration and also if retune is triggered at any time during operation. Update the printk level to pr_debug so that these errors don't lead to false error reports. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Cc: stable@vger.kernel.org # v4.4+ Link: https://lore.kernel.org/r/20191206114326.15856-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci: fix up CMD12 sendingYangbo Lu
The STOP command is disabled for multiple blocks r/w commands with auto CMD12, when start to send. However, if there is data error, software still needs to send CMD12 according to SD spec. This patch is to allow software CMD12 sending for this case. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191114111814.35199-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci: Update the tuning failed messages to pr_debug levelFaiz Abbas
Tuning support in DDR50 speed mode was added in SD Specifications Part1 Physical Layer Specification v3.01. Its not possible to distinguish between v3.00 and v3.01 from the SCR and that is why since commit 4324f6de6d2e ("mmc: core: enable CMD19 tuning for DDR50 mode") tuning failures are ignored in DDR50 speed mode. Cards compatible with v3.00 don't respond to CMD19 in DDR50 and this error gets printed during enumeration and also if retune is triggered at any time during operation. Update the printk level to pr_debug so that these errors don't lead to false error reports. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Cc: stable@vger.kernel.org # v4.4+ Link: https://lore.kernel.org/r/20191206114326.15856-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16Revert "mmc: sdhci: Fix incorrect switch to HS mode"Faiz Abbas
This reverts commit c894e33ddc1910e14d6f2a2016f60ab613fd8b37. This commit aims to treat SD High speed and SDR25 as the same while setting UHS Timings in HOST_CONTROL2 which leads to failures with some SD cards in AM65x. Revert this commit. The issue this commit was trying to fix can be implemented in a platform specific callback instead of common sdhci code. Cc: <stable@vger.kernel.org> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191128110422.25917-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-11-20mmc: sdhci: Fix grammar in warning messageFabio Estevam
The correct form is "did not become", so fix it accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-11-13mmc: sdhci: Check card status after resetRaul E Rangel
In sdhci_do_reset we call the reset callback which is typically sdhci_reset. sdhci_reset can wait for up to 100ms waiting for the controller to reset. If SDHCI_RESET_ALL was passed as the flag, the controller will clear the IRQ mask. If during that 100ms the card is removed there is no notification to the MMC system that the card was removed. So from the drivers point of view the card is always present. By making sdhci_reinit compare the present state it can schedule a rescan if the card was removed while a reset was in progress. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-27mmc: sdhci: Let drivers define their DMA maskAdrian Hunter
Add host operation ->set_dma_mask() so that drivers can define their own DMA masks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Cc: stable@vger.kernel.org # v4.15 + Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-27mmc: sdhci: improve ADMA error reportingRussell King
ADMA errors are potentially data corrupting events; although we print the register state, we do not usefully print the ADMA descriptors. Worse than that, we print them by referencing their virtual address which is meaningless when the register state gives us the DMA address of the failing descriptor. Print the ADMA descriptors giving their DMA addresses rather than their virtual addresses, and print them using SDHCI_DUMP() rather than DBG(). We also do not show the correct value of the interrupt status register; the register dump shows the current value, after we have cleared the pending interrupts we are going to service. What is more useful is to print the interrupts that _were_ pending at the time the ADMA error was encountered. Fix that too. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Convert to use sdio_irq_claimed()Ulf Hansson
Instead of keeping track of whether SDIO IRQs have been enabled via an internal sdhci status flag, avoid the open-coding and convert into using sdio_irq_claimed(). Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Drop redundant code for SDIO IRQsUlf Hansson
Nowadays sdhci prevents runtime suspend when SDIO IRQs are enabled. However, some variants such as sdhci-esdhc-imx's, tries to allow runtime suspend while having the SDIO IRQs enabled, but without supporting remote wakeups. This support is a bit questionable, especially if the host device have a PM domain attached that can be power gated, but more importantly, the code have also become redundant (which was not the case when it was introduced). Rather than keeping the redundant code around, let's drop it and leave this to be revisited later on. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq()Ulf Hansson
The sdhci_ack_sdio_irq() is called only when SDIO IRQs are enabled. Therefore, let's drop the redundant check of the internal SDHCI_SDIO_IRQ_ENABLED flag and just re-enable the IRQs immediately. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Fix incorrect switch to HS modeAl Cooper
When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: use lower/upper_32_bits() macros for DMA addressesMasahiro Yamada
Currently, the DMA addresses are casted to (u64) for the upper 32bits to avoid "right shift count >= width of type" warning. <linux/kernel.h> provides macros to address this, and I like the macro names are self-documenting. I introduced a new helper, sdhci_set_adma_addr() to avoid the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: constify references of parameters to __sdhci_read_caps()Masahiro Yamada
__sdhci_read_caps() does not modify *ver, *caps, or *caps1. Probably, the caller of this function will want to constifythe parameters passed in. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Export sdhci_abort_tuning function symbolBen Chuang
Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Add PLL Enable support to internal clock setupBen Chuang
The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Change timeout of loop for checking internal clock stableBen Chuang
According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-06mmc: sdhci-sprd: Fix the incorrect soft reset operation when runtime resumingBaolin Wang
The SD host controller specification defines 3 types software reset: software reset for data line, software reset for command line and software reset for all. Software reset for all means this reset affects the entire Host controller except for the card detection circuit. In sdhci_runtime_resume_host() we always do a software "reset for all", which causes the Spreadtrum variant controller to work abnormally after resuming. To fix the problem, let's do a software reset for the data and the command part, rather than "for all". However, as sdhci_runtime_resume() is a common sdhci function and we don't want to change the behaviour for other variants, let's introduce a new in-parameter for it. This enables the caller to decide if a "reset for all" shall be done or not. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-06-07Merge tag 'mmc-v5.2-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "Here's a couple of MMC and MEMSTICK fixes: MMC host: - sdhci: Fix SDIO IRQ thread deadlock - sdhci-tegra: Fix a warning message - sdhci_am654: Fix SLOTTYPE write - meson-gx: Fix IRQ ack - tmio: Fix SCC error handling to avoid false positive CRC error MEMSTICK core: - mspro_block: Fix returning a correct error code" * tag 'mmc-v5.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci_am654: Fix SLOTTYPE write mmc: sdhci: Fix SDIO IRQ thread deadlock mmc: meson-gx: fix irq ack mmc: tmio: fix SCC error handling to avoid false positive CRC error mmc: tegra: Fix a warning message memstick: mspro_block: Fix an error code in mspro_block_issue_req()
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-28mmc: sdhci: Fix SDIO IRQ thread deadlockAdrian Hunter
Since commit c07a48c26519 ("mmc: sdhci: Remove finish_tasklet"), the IRQ thread might be used to complete requests, but the IRQ thread is also used to process SDIO card interrupts. This can cause a deadlock when the SDIO processing tries to access the card since that would also require the IRQ thread. Change SDHCI to use sdio_signal_irq() to schedule a work item instead. That also requires implementing the ->ack_sdio_irq() mmc host op. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: c07a48c26519 ("mmc: sdhci: Remove finish_tasklet") Reported-by: Brian Masney <masneyb@onstation.org> Tested-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-07Merge tag 'mmc-v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmcLinus Torvalds
Pull MMC updates from Ulf Hansson: "MMC core: - Fix a few memoryleaks - Minor improvements to the card initialization sequence - Partially support sleepy GPIO controllers for pwrseq eMMC MMC host: - alcor: Work with multiple-entry sglists - alcor: Enable DMA for writes - meson-gx: Improve tuning support - meson-gx: Avoid clock glitch when switching to DDR modes - meson-gx: Disable unreliable HS400 mode - mmci: Minor updates for support of HW busy detection - mmci: Support data transfers for the stm32_sdmmc variant - mmci: Restructure code to better support different variants - mtk-sd: Add support for version found on MT7620 family SOCs - mtk-sd: Add support for the MT8516 version - mtk-sd: Add Chaotian Jing as the maintainer - sdhci: Reorganize request-code to convert from tasklet to workqueue - sdhci_am654: Stabilize support for lower speed modes - sdhci-esdhc-imx: Add HS400 support for iMX7ULP - sdhci-esdhc-imx: Add support for iMX7ULP version - sdhci-of-arasan: Allow to disable DCMDs via DT for CQE - sdhci-of-esdhc: Add support for the ls1028a version - sdhci-of-esdhc: Several fixups for errata - sdhci-pci: Fix BYT OCP setting - sdhci-pci: Add support for Intel CML - sdhci-tegra: Add support for system suspend/resume - sdhci-tegra: Add CQE support for Tegra186 WAR - sdhci-tegra: Add support for Tegra194 - sdhci-tegra: Update HW tuning process MEMSTICK: - I volunteered to help as a maintainer for the memstick subsystem, which is reflected by an update to the MAINTAINERS file. Changes are funneled through my MMC git and we will use the linux-mmc mailing list. MEMSTICK host: - A few minor cleanups" * tag 'mmc-v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (87 commits) mmc: sdhci-pci: Fix BYT OCP setting dt-bindings: mmc: add DT bindings for ls1028a eSDHC host controller mmc: alcor: Drop pointer to mmc_host from alcor_sdmmc_host mmc: mtk-sd: select REGULATOR mmc: mtk-sd: enable internal card-detect logic. mmc: mtk-sd: add support for config found in mt7620 family SOCs. mmc: mtk-sd: don't hard-code interrupt trigger type mmc: core: Fix tag set memory leak dt-bindings: mmc: Add support for MT8516 to mtk-sd mmc: mmci: Prevent polling for busy detection in IRQ context mmc: mmci: Cleanup mmci_cmd_irq() for busy detect mmc: usdhi6rol0: mark expected switch fall-throughs mmc: core: Verify SD bus width mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string mmc: meson-gx: add signal resampling tuning mmc: meson-gx: remove Rx phase tuning mmc: meson-gx: avoid clock glitch when switching to DDR modes mmc: meson-gx: disable HS400 ...
2019-04-15mmc: sdhci: Remove finish_taskletAdrian Hunter
Remove finish_tasklet. Requests that require DMA-unmapping or sdhci_reset are completed either in the IRQ thread or a workqueue if the completion is not initiated by the IRQ. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: sdhci: Call mmc_request_done() from IRQ handler if possibleAdrian Hunter
In preparation for removing finish_tasklet, call mmc_request_done() from the IRQ handler if possible. That will alleviate the potential loss of performance from shifting away from finish_tasklet. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: sdhci: Move some processing to __sdhci_finish_mrq()Adrian Hunter
In preparation for removing finish_tasklet, move some processing from sdhci_request_done() to __sdhci_finish_mrq(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: sdhci: Move timer and has_requests functionsAdrian Hunter
In preparation for removing finish_tasklet, move some functions. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: sdhci: Reorganize sdhci_finish_mrq() and __sdhci_finish_mrq()Adrian Hunter
In preparation for removing finish_tasklet, reorganize sdhci_finish_mrq() and __sdhci_finish_mrq() to separate the tasklet scheduling from other processing. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: sdhci: allow host to specify maximum tuning loopsSowjanya Komatineni
As per the Host Controller Standard Specification Version 4.20, limitation of tuning iteration count is removed as PLL locking time can be longer than UHS-1 tuning due to larger PVT fluctuation and it will result in increase of tuning iteration to complete the tuning. This patch creates sdhci_host member tuning_loop_count to allow hosts to specify maximum tuning iterations and also updates execute_tuning to use this specified maximum tuning iteration count. Default tuning_loop_count is set to same as existing loop count of MAX_TUNING_LOOP which is 40 iterations. Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-08drivers: Remove explicit invocations of mmiowb()Will Deacon
mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-02-25mmc: sdhci: use WP GPIO in sdhci_check_ro()Thomas Petazzoni
Even though SDHCI controllers may have a dedicated WP pin that can be queried using the SDHCI_PRESENT_STATE register, some platforms may chose to use a separate regular GPIO to route the WP signal. Such a GPIO is typically represented using the wp-gpios property in the Device Tree. Unfortunately, the current sdhci_check_ro() function does not make use of such GPIO when available: it either uses a host controller specific ->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host controller specific ->get_ro() functions are implemented just to check a WP GPIO state. Instead of pushing this to more controller-specific implementations, let's handle this in the core SDHCI code, just like it is already done for the CD GPIO in sdhci_get_cd(). The below patch simply changes sdhci_check_ro() to use the value of the WP GPIO if available. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: Add ADMA3 DMA support for V4 enabled hostSowjanya Komatineni
Below are the supported DMA types in Host Control1 Register with Version 4 enable b'00 - SDMA b'01 - Not Used b'10 - ADMA2 b'11 - ADMA2 or ADMA3 ADMA3 uses Command Descriptor to issue an SD command. A multi-block data transfer is performed by using a pair of CMD descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using Integrated Descriptor which is more suitable for Command Queuing to fetch both Command and Transfer descriptors. Host Capabilities register indicates the supports of ADMA3 DMA. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: correct the maximum timeout when enable CMDQBOUGH CHEN
Change to use sdhci_set_timeout() to set the maximum timeout, so that the host can use it's own set_timeout() callback to set the maximum timeout if the host has. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: add delay after the last tuning commandBOUGH CHEN
When host set the host->tuning_delay, even the last tuning command need a delay, otherwise the first command after the tuning will meet issue. Take i.MX7D as an example, there will be the following log: mmc2: switch to high-speed from hs200 failed, err:-110 mmc2: error -110 whilst initialising MMC card Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-01-08cross-tree: phase out dma_zalloc_coherent()Luis Chamberlain
We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>
2018-12-17Merge branch 'fixes' into nextUlf Hansson
2018-12-17mmc: sdhci: Fix sdhci_do_enable_v4_modeSowjanya Komatineni
V4_MODE is Bit-15 of SDHCI_HOST_CONTROL2 register. Need to perform word access to this register. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Fixes: b3f80b434f72 ("mmc: sdhci: Add sd host v4 mode") Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci: Add quirk to disable LED controlAdrian Hunter
Host controllers may not have a LED signal line, whereas the register updates to control the non-existent LED can be relatively time consuming. Add a quirk to disable LED control. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci: Handle auto-command errorsAdrian Hunter
If the host controller supports auto-commands then enable the auto-command error interrupt and handle it. In the case of auto-CMD23, the error is treated the same as manual CMD23 error. In the case of auto-CMD12, commands-during-transfer are not permitted, so the error handling is treated the same as a data error. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci: Rename SDHCI_ACMD12_ERR and SDHCI_INT_ACMD12ERRAdrian Hunter
The SDHCI_ACMD12_ERR register is used for auto-CMD23 and auto-CMD12 errors, as is the SDHCI_INT_ACMD12ERR interrupt bit. Rename them to SDHCI_AUTO_CMD_STATUS and SDHCI_INT_AUTO_CMD_ERR respectively. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit (git 2.34.1) at 2024-05-24 20:14:19 +0000