summaryrefslogtreecommitdiff
path: root/drivers/mtd/spi-nor/spi-nor.c
AgeCommit message (Collapse)Author
2019-04-01spi-nor: s25fl512s supports region lockingJonas Bonn
Both the BP[0-2] bits and the TBPROT bit are supported on this chip. Tested and verified on a Cypress s25fl512s. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: spi-nor: Fix comment of spi_nor_find_best_erase_type()Alexander Sverdlin
Erase types are sorted *smallest* type first, refer to spi_nor_sort_erase_mask(). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: spi-nor: Print all JEDEC ID bytes on errorGeert Uytterhoeven
If identification of an SPI NOR FLASH fails, the JEDEC ID is printed, which is stored in the first 3 bytes of the ID read from the FLASH. However, the extended JEDEC ID, which is stored in the remaining bytes, also matters, as it is used for identification of some FLASH types. Print all (currently 6) ID bytes read to ease failure analysis and debugging. Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-02-21mtd: spi-nor: Add support for en25qh64Roger Pueyo Centelles
The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found on recent wireless routers. Its 32, 128 and 256 Mbit siblings are already supported. Tested on a COMFAST CF-E120A v3 router board. Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21mtd: spi-nor: Add support for MX25V8035FFrieder Schrempf
This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip. It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21mtd: spi-nor: Add support for EN25Q80AFrieder Schrempf
This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. It is used on i.MX6 boards by Kontron Electronics GmbH (N60xx, N61xx). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-13mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1Ahmet Celenk
Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of the s25fl128s qspi memory, the single "s25fl128s" device entry must be split into two to match the correct JEDEC ID's for each version. Solves paging related issues of S25FL128SAGBHI210 chips. Signed-off-by: Ahmet Celenk <ahmet.celenk@procenne.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-10mtd: spi-nor: Add support for mx25u3235fAndré Valentin
The mx25u3235f is found on the ZyXEL NBG6817 router, therefore add driver support for it so that we can upstream board support. Minimal tested with u-boot tools fw_printenv/fw_setenv on GlobalScale ESPRESSObin v5 board. Signed-off-by: André Valentin <avalentin@marcant.net> [miyatsu@qq.com: Remove unnecessary white space.] Signed-off-by: Ding Tao <miyatsu@qq.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-01-23mtd: spi-nor: refine Spansion S25FL512S IDSergei Shtylyov
Spansion S25FL512S ID is erroneously using 5-byte JEDEC ID, while the chip family ID is stored in the 6th byte. Due to using only 5-byte ID, it's also covering S25FS512S and now that we have added 6-byte ID for that chip, we can convert S25FL512S to using a proper 6-byte ID as well... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
2019-01-23mtd: spi-nor: add Spansion S25FS512S IDSergei Shtylyov
Spansion S25FS512S flash is currently misdetected as S25FL512S since the latter uses 5-byte JEDEC ID, while the 6th ID byte (family ID) is different on those chips. Add the 6-byte S25FS512S ID before S25FL512S ID in order not to break the existing S25FS512S users. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
2019-01-17mtd: spi-nor: add octal read flag for flash mt35xu512abaYogesh Narayan Gaur
Add octal read flag for flash mt35xu512aba. This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does not seem to support newer JESD216C standard that provides auto detection of Octal mode capabilities and opcodes. Therefore, this capability is manually added using new SPI_NOR_OCTAL_READ flag. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
2019-01-17mtd: spi-nor: add opcodes for octal Read/Write commandsYogesh Narayan Gaur
- Add opcodes for octal I/O commands * Read : 1-1-8 and 1-8-8 protocol * Write : 1-1-8 and 1-8-8 protocol * opcodes for 4-byte address mode command - Entry of macros in _convert_3to4_xxx function - Add flag SPI_NOR_OCTAL_READ specifying flash support octal read commands. This flag is required for flashes which didn't provides support for auto detection of Octal mode capabilities i.e. not seems to support newer JESD216C standard. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
2018-12-10mtd: spi-nor: Add support for is25lp016dFabrizio Castro
The is25lp016d is found on the iwg23s from iWave, therefore add driver support for it so that we can upstream board support. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: parse SFDP 4-byte Address Instruction TableCyrille Pitchen
Add support for SFDP (JESD216B) 4-byte Address Instruction Table. This table is optional but when available, we parse it to get the 4-byte address op codes supported by the memory. Using these op codes is stateless as opposed to entering the 4-byte address mode or setting the Base Address Register (BAR). Flashes that have the 4BAIT table declared can now support SPINOR_OP_PP_1_1_4_4B and SPINOR_OP_PP_1_4_4_4B opcodes. Tested on MX25L25673G. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> [tudor.ambarus@microchip.com: - rework erase and page program logic, - pass DMA-able buffer to spi_nor_read_sfdp(), - introduce SPI_NOR_HAS_4BAIT - various minor updates.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: Add 4B_OPCODES flag to is25lp256Liu Xiang
The is25lp256 supports 4-byte opcodes and quad output. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: Add an SPDX tag to spi-nor.{c,h}Boris Brezillon
Add SPDX tags to replace the license boiler-plate and fix the MODULE_LICENSE() definition in spi-nor.c to match the license text (GPL v2). Interestingly, spi-nor.h and spi-nor.c do not use the same license (GPL v2+ for spi-nor.h, GPL v2 for spi-nor.c). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Make the enable argument passed to set_byte() a boolBoris Brezillon
No need to use an integer when the value is either true or false. Make it a boolean. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Stop passing flash_info aroundBoris Brezillon
Some functions called from spi_nor_scan() need a flash_info object. Let's assign nor->info early on to avoid passing info as an extra argument to each of these sub-functions. We also stop passing a flash_info object to set_4byte() and use nor->info directly. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Avoid forward declaration of internal functionsBoris Brezillon
Reorganize the code to kill forward declarations of spi_nor_match_id() macronix_quad_enable() and spi_nor_hwcaps_read2cmd(). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Drop inline on all internal helpersBoris Brezillon
gcc should be smart enough to decide when inlining a function makes sense. Drop all inline specifiers. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Add a post BFPT fixup for MX25L25635EBoris Brezillon
MX25L25635F and MX25L25635E share the same JEDEC-ID, but the F variant supports 4-byte opcodes while the E variant doesn't. We need a way to differentiate those 2 chips and set the SNOR_F_4B_OPCODES flag only for the F variant. Luckily, 4-byte opcode support is not the only difference: Fast Read 4-4-4 is only supported by the F variant, and this feature is advertised in the BFPT table. Use this to decide when to set the SNOR_F_4B_OPCODES flag. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Add a post BFPT parsing fixup hookBoris Brezillon
Experience has proven that SFDP tables are sometimes wrong, and parsing of these broken tables can lead to erroneous flash config. This leaves us 2 options: 1/ set the SPI_NOR_SKIP_SFDP flag and completely ignore SFDP parsing 2/ fix things at runtime While #1 should always work, it might imply extra work if most of the SFDP is correct. #2 has the benefit of keeping the generic SFDP parsing logic almost untouched while allowing SPI NOR manufacturer drivers to fix the broken bits. Add a spi_nor_fixups struct where we'll put all our fixup hooks, each of them being called at a different point in the scan process. We start a hook called just after the BFPT parsing to allow fixing up info extracted from the BFPT section. More hooks will be added if other sections need to be fixed. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: Add the SNOR_F_4B_OPCODES flagBoris Brezillon
Some flash_info entries have the SPI_NOR_4B_OPCODES flag set to let the core know that the flash supports 4B opcode. While this solution works fine for id-based caps detection, it doesn't work that well when relying on SFDP-based caps detection. Let's add an SNOR_F_4B_OPCODES flag so that the SFDP parsing code can set it when appropriate. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-12-10mtd: spi-nor: cast to u64 to avoid uint overflowshuijin.park
The "params->size" is defined as "u64". And "info->sector_size" and "info->n_sectors" are defined as unsigned int and u16. Thus, u64 data might have strange data(loss data) if the result overflows an unsigned int. This patch casts "info->sector_size" to an u64. Signed-off-by: huijin.park <huijin.park@samsung.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: Add support for IS25LP032/064Uwe Kleine-König
The datasheet is publically available at http://www.issi.com/WW/pdf/IS25LP032-064-128.pdf. The parameters fit to what is already available for IS25LP128/256. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: add entry for mt35xu512aba flashYogesh Narayan Gaur
Add entry for mt35xu512aba Micron NOR flash. This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: add macros related to MICRON flashYogesh Narayan Gaur
Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: mark desirable switch case fall throughTudor.Ambarus@microchip.com
gcc 7 with -Wimplicit-fallthrough raises: drivers/mtd/spi-nor/spi-nor.c: In function ‘set_4byte’: drivers/mtd/spi-nor/spi-nor.c:289:13: warning: this statement may fall through [-Wimplicit-fallthrough=] need_wren = true; ~~~~~~~~~~^~~~~~ drivers/mtd/spi-nor/spi-nor.c:290:2: note: here case SNOR_MFR_MACRONIX: ^~~~ Quiet the warning by marking the expected switch fall through. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: Add support for mx25u12835fAlexander Sverdlin
This chip supports dual and quad read and uniform 4K-byte erase. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: Add Winbond w25q128jv supportRobert Marko
Datasheet: http://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf Testing done on Mikrotik Routerboard wAP R board. It does not support Dual or Quad modes. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-12-10mtd: spi-nor: remove unneeded smpt zeroizationTudor.Ambarus@microchip.com
The entire smpt array is initialized with data read from sfdp, there is no need to init it with zeroes before. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-28mtd: spi-nor: fix erase_type array to indicate current map confTudor Ambarus
BFPT advertises all the erase types supported by all the possible map configurations. Mask out the erase types that are not supported by the current map configuration. Backward compatibility test done on sst26vf064b. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Reported-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-20mtd: spi-nor: fix selection of uniform erase type in flexible confTudor.Ambarus@microchip.com
There are uniform, non-uniform and flexible erase flash configurations. The non-uniform erase types, are the erase types that can _not_ erase the entire flash by their own. As the code was, in case flashes had flexible erase capabilities (support both uniform and non-uniform erase types in the same flash configuration) and supported multiple uniform erase type sizes, the code did not sort the uniform erase types, and could select a wrong erase type size. Sort the uniform erase mask in case of flexible erase flash configurations, in order to select the best uniform erase type size. Uniform, non-uniform, and flexible configurations with just a valid uniform erase type, are not affected by this change. Uniform erase tested on mx25l3273fm2i-08g and sst26vf064B-104i/sn. Non uniform erase tested on sst26vf064B-104i/sn. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-13mtd: spi_nor: pass DMA-able buffer to spi_nor_read_raw()Tudor.Ambarus@microchip.com
spi_nor_read_raw() calls nor->read() which might be implemented by the m25p80 driver. m25p80 uses the spi-mem layer which requires DMA-able in/out buffers. Pass kmalloc'ed dma buffer to spi_nor_read_raw(). Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-13mtd: spi-nor: don't overwrite errno in spi_nor_get_map_in_use()Tudor.Ambarus@microchip.com
Don't overwrite the errno from spi_nor_read_raw(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-13mtd: spi-nor: fix iteration over smpt arrayTudor.Ambarus@microchip.com
Iterate over smpt array using its starting address and length instead of the blind iterations that used data found in the array. This prevents possible memory accesses outside of the smpt array boundaries in case software, or manufacturers, misrepresent smpt array fields. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-13mtd: spi-nor: don't drop sfdp data if optional parsers failTudor.Ambarus@microchip.com
JESD216C states that just the Basic Flash Parameter Table is mandatory. Already defined (or future) additional parameter headers and tables are optional. Don't drop already collected sfdp data in case an optional table parser fails. In case of failing, each optional parser is responsible to roll back to the previously known spi_nor data. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Reported-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-11-05mtd: spi-nor: Reset nor->addr_width when SFDP parsing failedBoris Brezillon
Commit 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") removed the 'nor->addr_width = 0;' statement when spi_nor_parse_sfdp() returns an error, thus leaving ->addr_width in an undefined state which can cause trouble when spi_nor_scan() checks its value. Reported-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2018-10-08mtd: spi-nor: Support controllers with limited TX FIFO sizeYogesh Gaur
Some SPI controllers can't write nor->page_size bytes in a single step because their TX FIFO is too small. Allow nor->write() to return a size that is smaller than the requested write size to gracefully handle this case. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-08mtd: spi-nor: parse SFDP Sector Map Parameter TableTudor Ambarus
Add support for the SFDP (JESD216B) Sector Map Parameter Table. This table is optional, but when available, we parse it to identify the location and size of sectors within the main data array of the flash memory device and to identify which Erase Types are supported by each sector. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-08mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memoriesTudor Ambarus
Based on Cyrille Pitchen's patch https://lkml.org/lkml/2017/3/22/935. This patch is a transitional patch in introducing the support of SFDP SPI memories with non-uniform erase sizes like Spansion s25fs512s. Non-uniform erase maps will be used later when initialized based on the SFDP data. Introduce the memory erase map which splits the memory array into one or many erase regions. Each erase region supports up to 4 erase types, as defined by the JEDEC JESD216B (SFDP) specification. To be backward compatible, the erase map of uniform SPI NOR flash memories is initialized so it contains only one erase region and this erase region supports only one erase command. Hence a single size is used to erase any sector/block of the memory. Besides, since the algorithm used to erase sectors on non-uniform SPI NOR flash memories is quite expensive, when possible, the erase map is tuned to come back to the uniform case. The 'erase with the best command, move forward and repeat' approach was suggested by Cristian Birsan in a brainstorm session, so: Suggested-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-08-01mtd: spi-nor: only apply reset hacks to broken hardwareBrian Norris
Commit 59b356ffd0b0 ("mtd: m25p80: restore the status of SPI flash when exiting") is the latest from a long history of attempts to add reboot handling to handle stateful addressing modes on SPI flash. Some prior mostly-related discussions: http://lists.infradead.org/pipermail/linux-mtd/2013-March/046343.html [PATCH 1/3] mtd: m25p80: utilize dedicated 4-byte addressing commands http://lists.infradead.org/pipermail/barebox/2014-September/020682.html [RFC] MTD m25p80 3-byte addressing and boot problem http://lists.infradead.org/pipermail/linux-mtd/2015-February/057683.html [PATCH 2/2] m25p80: if supported put chip to deep power down if not used Previously, attempts to add reboot-time software reset handling were rejected, but the latest attempt was not. Quick summary of the problem: Some systems (e.g., boot ROM or bootloader) assume that they can read initial boot code from their SPI flash using 3-byte addressing. If the flash is left in 4-byte mode after reset, these systems won't boot. The above patch provided a shutdown/remove hook to attempt to reset the addressing mode before we reboot. Notably, this patch misses out on huge classes of unexpected reboots (e.g., crashes, watchdog resets). Unfortunately, it is essentially impossible to solve this problem 100%: if your system doesn't know how to reset the SPI flash to power-on defaults at initialization time, no amount of software can really rescue you -- there will always be a chance of some unexpected reset that leaves your flash in an addressing mode that your boot sequence didn't expect. While it is not directly harmful to perform hacks like the aforementioned commit on all 4-byte addressing flash, a properly-designed system should not need the hack -- and in fact, providing this hack may mask the fact that a given system is indeed broken. So this patch attempts to apply this unsound hack more narrowly, providing a strong suggestion to developers and system designers that this is truly a hack. With luck, system designers can catch their errors early on in their development cycle, rather than applying this hack long term. But apparently enough systems are out in the wild that we still have to provide this hack. Document a new device tree property to denote systems that do not have a proper hardware (or software) reset mechanism, and apply the hack (with a loud warning) only in this case. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-05-18mtd: spi-nor: Add support for EN25QH32YuheiOKAWA
Add support for Eon en25qh32 spi nor flash. Signed-off-by: YuheiOKAWA <tochiro.srchack@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-05-18mtd: spi-nor: Add support for is25wp series chipsKimmo Rautkoski
Added support for is25wp032, is25wp064 and is25wp128. Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-05-18mtd: spi-nor: Add Winbond w25q32jv supportStephen Douthit
Datasheet: https://www.winbond.com/resource-files/w25q32jv%20dtr%20revf%2002242017.pdf Minimal testing done with fw_printenv/fw_setenv, test board did not support dual or quad access. Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Tested-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-04-21mtd: spi-nor: clear Winbond Extended Address Reg on switch to 3-byte addressing.NeilBrown
Winbond spi-nor flash 32MB and larger have an 'Extended Address Register' as one option for addressing beyond 16MB (Macronix has the same concept, Spansion has EXTADD bits in the Bank Address Register). According to section 8.2.7 Write Extended Address Register (C5h) of the Winbond W25Q256FV data sheet (256M-BIT SPI flash) The Extended Address Register is only effective when the device is in the 3-Byte Address Mode. When the device operates in the 4-Byte Address Mode (ADS=1), any command with address input of A31-A24 will replace the Extended Address Register values. It is recommended to check and update the Extended Address Register if necessary when the device is switched from 4-Byte to 3-Byte Address Mode. So the documentation suggests clearing the EAR after switching to 3-byte mode. Experimentation shows that the EAR is *always* one after the switch to 3-byte mode, so clearing the EAR is mandatory at shutdown for a subsequent 3-byte-addressed reboot to work. Note that some SOCs (e.g. MT7621) do not assert a reset line at normal reboot, so we cannot rely on hardware reset. The MT7621 does assert a reset line at watchdog-reset. Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: NeilBrown <neil@brown.name> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-04-20mtd: spi-nor: Add support for XM25QH64A and XM25QH128AHauke Mehrtens
These devices are produced by Wuhan Xinxin Semiconductor Manufacturing Corp. (XMC) and found on some routers from Chinese manufactures. The data sheets can be found here: http://www.xmcwh.com/Uploads/2018-03-01/5a9799e4cb355.pdf http://www.xmcwh.com/Uploads/2018-02-05/5a77e6dbe968b.pdf Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-04-20mtd: spi-nor: add support for ISSI is25lp256Marek Vasut
Add support for ISSI is25lp256 spi nor flash. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-04-20mtd: spi-nor: Add Micron MT25QU02 supportThor Thayer
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf Testing was done on a Stratix10 SoCFPGA Development Kit. Reported-by: Sujith Chidurala <sujith.chakra.chidurala@intel.com> Tested-by: Paul Kim <paul.kim@intel.com> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-03-21mtd: Stop updating erase_info->state and calling mtd_erase_callback()Boris Brezillon
MTD users are no longer checking erase_info->state to determine if the erase operation failed or succeeded. Moreover, mtd_erase_callback() is now a NOP. We can safely get rid of all mtd_erase_callback() calls and all erase_info->state assignments. While at it, get rid of the erase_info->state field, all MTD_ERASE_XXX definitions and the mtd_erase_callback() function. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Richard Weinberger <richard@nod.at> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Bert Kenward <bkenward@solarflare.com> --- Changes in v2: - Address a few coding style issues (reported by Miquel) - Remove comments that are no longer valid (reported by Miquel)
generated by cgit (git 2.34.1) at 2024-07-06 20:57:36 +0000