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2019-12-03Merge tag 'tty-5.5-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty/serial updates from Greg KH: "Here is the "big" tty and serial driver patches for 5.5-rc1. It's a bit later in the merge window than normal as I wanted to make sure some last-minute patches applied to it were all sane. They seem to be :) There's a lot of little stuff in here, for the tty core, and for lots of serial drivers: - reverts of uartlite serial driver patches that were wrong - msm-serial driver fixes - serial core updates and fixes - tty core fixes - serial driver dma mapping api changes - lots of other tiny fixes and updates for serial drivers All of these have been in linux-next for a while with no reported issues" * tag 'tty-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (58 commits) Revert "serial/8250: Add support for NI-Serial PXI/PXIe+485 devices" vcs: prevent write access to vcsu devices tty: vt: keyboard: reject invalid keycodes tty: don't crash in tty_init_dev when missing tty_port serial: stm32: fix clearing interrupt error flags tty: Fix Kconfig indentation, continued serial: serial_core: Perform NULL checks for break_ctl ops tty: remove unused argument from tty_open_by_driver() tty: Fix Kconfig indentation {tty: serial, nand: onenand}: samsung: rename to fix build warning serial: ifx6x60: add missed pm_runtime_disable serial: pl011: Fix DMA ->flush_buffer() Revert "serial-uartlite: Move the uart register" Revert "serial-uartlite: Add get serial id if not provided" Revert "serial-uartlite: Do not use static struct uart_driver out of probe()" Revert "serial-uartlite: Add runtime support" Revert "serial-uartlite: Change logic how console_port is setup" Revert "serial-uartlite: Use allocated structure instead of static ones" tty: serial: msm_serial: Use dma_request_chan() directly for channel request tty: serial: tegra: Use dma_request_chan() directly for channel request ...
2019-12-02Merge tag 'upstream-5.5-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI/UBIFS/JFFS2 updates from Richard Weinberger: "This pull request contains mostly fixes for UBI, UBIFS and JFFS2: UBI: - Fix a regression around producing a anchor PEB for fastmap. Due to a change in our locking fastmap was unable to produce fresh anchors an re-used the existing one a way to often. UBIFS: - Fixes for endianness. A few places blindly assumed little endian. - Fix for a memory leak in the orphan code. - Fix for a possible crash during a commit. - Revert a wrong bugfix. JFFS2: - Revert a bad bugfix (false positive from a code checking tool)" * tag 'upstream-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: Revert "jffs2: Fix possible null-pointer dereferences in jffs2_add_frag_to_fragtree()" ubi: Fix producing anchor PEBs ubifs: ubifs_tnc_start_commit: Fix OOB in layout_in_gaps ubifs: do_kill_orphans: Fix a memory leak bug Revert "ubifs: Fix memory leak bug in alloc_ubifs_info() error path" ubifs: Fix type of sup->hash_algo ubifs: Fixed missed le64_to_cpu() in journal ubifs: Force prandom result to __le32 ubifs: Remove obsolete TODO from dfs_file_write() ubi: Fix warning static is not at beginning of declaration ubi: Print skip_check in ubi_dump_vol_info()
2019-12-01Merge tag 'compat-ioctl-5.5' of ↵Linus Torvalds
git://git.kernel.org:/pub/scm/linux/kernel/git/arnd/playground Pull removal of most of fs/compat_ioctl.c from Arnd Bergmann: "As part of the cleanup of some remaining y2038 issues, I came to fs/compat_ioctl.c, which still has a couple of commands that need support for time64_t. In completely unrelated work, I spent time on cleaning up parts of this file in the past, moving things out into drivers instead. After Al Viro reviewed an earlier version of this series and did a lot more of that cleanup, I decided to try to completely eliminate the rest of it and move it all into drivers. This series incorporates some of Al's work and many patches of my own, but in the end stops short of actually removing the last part, which is the scsi ioctl handlers. I have patches for those as well, but they need more testing or possibly a rewrite" * tag 'compat-ioctl-5.5' of git://git.kernel.org:/pub/scm/linux/kernel/git/arnd/playground: (42 commits) scsi: sd: enable compat ioctls for sed-opal pktcdvd: add compat_ioctl handler compat_ioctl: move SG_GET_REQUEST_TABLE handling compat_ioctl: ppp: move simple commands into ppp_generic.c compat_ioctl: handle PPPIOCGIDLE for 64-bit time_t compat_ioctl: move PPPIOCSCOMPRESS to ppp_generic compat_ioctl: unify copy-in of ppp filters tty: handle compat PPP ioctls compat_ioctl: move SIOCOUTQ out of compat_ioctl.c compat_ioctl: handle SIOCOUTQNSD af_unix: add compat_ioctl support compat_ioctl: reimplement SG_IO handling compat_ioctl: move WDIOC handling into wdt drivers fs: compat_ioctl: move FITRIM emulation into file systems gfs2: add compat_ioctl support compat_ioctl: remove unused convert_in_user macro compat_ioctl: remove last RAID handling code compat_ioctl: remove /dev/raw ioctl translation compat_ioctl: remove PCI ioctl translation compat_ioctl: remove joystick ioctl translation ...
2019-11-18{tty: serial, nand: onenand}: samsung: rename to fix build warningSudip Mukherjee
Any arm config which has 'CONFIG_MTD_ONENAND_SAMSUNG=m' and 'CONFIG_SERIAL_SAMSUNG=m' gives a build warning: warning: same module names found: drivers/tty/serial/samsung.ko drivers/mtd/nand/onenand/samsung.ko Rename both drivers/tty/serial/samsung.c to drivers/tty/serial/samsung_tty.c and drivers/mtd/nand/onenand/samsung.c drivers/mtd/nand/onenand/samsung_mtd.c to fix the warning. Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Acked-by: Richard Weinberger <richard@nod.at> Link: https://lore.kernel.org/r/20191117202435.28127-1-sudipm.mukherjee@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-11-17ubi: Fix producing anchor PEBsSascha Hauer
When a new fastmap is about to be written UBI must make sure it has a free block for a fastmap anchor available. For this ubi_update_fastmap() calls ubi_ensure_anchor_pebs(). This stopped working with 2e8f08deabbc ("ubi: Fix races around ubi_refill_pools()"), with this commit the wear leveling code is blocked and can no longer produce free PEBs. UBI then more often than not falls back to write the new fastmap anchor to the same block it was already on which means the same erase block gets erased during each fastmap write and wears out quite fast. As the locking prevents us from producing the anchor PEB when we actually need it, this patch changes the strategy for creating the anchor PEB. We no longer create it on demand right before we want to write a fastmap, but instead we create an anchor PEB right after we have written a fastmap. This gives us enough time to produce a new anchor PEB before it is needed. To make sure we have an anchor PEB for the very first fastmap write we call ubi_ensure_anchor_pebs() during initialisation as well. Fixes: 2e8f08deabbc ("ubi: Fix races around ubi_refill_pools()") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-11-17ubi: Fix warning static is not at beginning of declarationRishi Gupta
Compiler generates following warning when kernel is built with W=1: drivers/mtd/ubi/ubi.h:971:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration] This commit fixes this by correctly ordering keywords. Signed-off-by: Rishi Gupta <gupt21@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-11-17ubi: Print skip_check in ubi_dump_vol_info()Stefan Roese
It might be interesting, if "skip_check" is set or not, so lets print this flag in ubi_dump_vol_info() as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Weinberger <richard@nod.at> Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-11-17Merge tag 'nand/for-5.5' into mtd/nextMiquel Raynal
Raw NAND core * Useless extra checks dropped. * Updated the detection of the bad block markers position Raw NAND controller drivers: * Cadence : New driver * Brcmnand: Support for flash-dma v0 + fixes * Denali : Support for the legacy controller/chip DT representation dropped * Superfluous dev_err() calls removed
2019-11-17Merge tag 'spi-nor/for-5.5' into mtd/nextMiquel Raynal
SPI NOR core changes: - introduce 'struct spi_nor_controller_ops', - clean the Register Operations methods, - use dev_dbg insted of dev_err for low level info, - fix retlen handling in sst_write(), - fix silent truncations in spi_nor_read and spi_nor_read_raw(), - fix the clearing of QE bit on lock()/unlock(), - rework the disabling of the block write protection, - rework the Quad Enable methods, - make sure nor->spimem and nor->controller_ops are mutually exclusive, - set default Quad Enable method for ISSI flashes, - add support for few flashes. SPI NOR controller drivers changes: - intel-spi: - support chips without software sequencer, - add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
2019-11-17Merge CFI/Hyperbus tag 'for-v5.5-rc1' into mtd/nextMiquel Raynal
CFI core changes: * Code cleanups related useless initializers and coding style issues * Fix for a possible double free problem in cfi_cmdset_0002 * Improved error reporting and handling in cfi_cmdset_0002 core for HyperFlash
2019-11-14mtd: devices: fix mchp23k256 read and writeAngelo Dureghello
Due to the use of sizeof(), command size set for the spi transfer was wrong. Driver was sending and receiving always 1 byte less and especially on write, it was hanging. echo -n -e "\\x1\\x2\\x3\\x4" > /dev/mtd1 And read part too now works as expected. hexdump -C -n16 /dev/mtd1 00000000 01 02 03 04 ab f3 ad c2 ab e3 f4 36 dd 38 04 15 00000010 Fixes: 4379075a870b ("mtd: mchp23k256: Add support for mchp23lcv1024") Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-11-14mtd: no need to check return value of debugfs_create functionsGreg Kroah-Hartman
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Artem Bityutskiy <dedekind1@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-11-11mtd: spi-nor: Set default Quad Enable method for ISSI flashesSagar Shrikant Kadam
Set the default Quad Enable method for ISSI flashes. Used for ISSI flashes (IS25WP256D-JMLE) that do not support SFDP tables and can not determine the Quad Enable method by parsing BFPT. Based on code originally written by Wesley Terpstra <wesley@sifive.com> and/or Palmer Dabbelt <palmer@sifive.com> https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> [tudor.ambarus@microchip.com: - rebase, split and adapt for latest spi-nor/next, - use PMC CFI ID for ISSI. According to JEP106BA, "Programmable Micro Corp" changed its name to Integrated Silicon Solution (ISSI)] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Add support for is25wp256Sagar Shrikant Kadam
Update the spi_nor_id table for is25wp256 (32MB) device from ISSI, present on HiFive Unleashed dev board (Rev: A00). Use the post bfpt fixup hook for the is25wp256 device, as done for the is25lp256 device to overwrite the wrong address width advertised by BFPT. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> [tudor.ambarus@microchip.com: rebase, split and adapt for latest spi-nor/next] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Add support for w25q256jwManivannan Sadhasivam
Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip supports dual/quad I/O mode with 512 blocks of memory organized in 64KB sectors. In addition to this, there is also small 4KB sectors available for flexibility. The device has been validated using Thor96 board. Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Darshak Patel <darshak.patel@einfochips.com> [Mani: cleaned up for upstream] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-11mtd: spi-nor: Move condition to avoid a NULL checkTudor Ambarus
When the controller is not under the SPI-MEM interface it may implement the optional controller_ops->erase() method. nor->spimem and nor->controller_ops are mutually exclusive. Move the nor->controller_ops->erase != NULL check as an 'else if' case to nor->spimem, in order to avoid the nor->controller_ops != NULL check. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-11mtd: spi-nor: Make sure nor->spimem and nor->controller_ops are mutually ↵Tudor Ambarus
exclusive Expand the spi_nor_check() to make sure that nor->spimem and nor->controller_ops are mutually exclusive. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-11mtd: spi-nor: Rename Quad Enable methodsTudor Ambarus
Rename macronix_quad_enable() to a generic name: spi_nor_sr1_bit6_quad_enable(). Prepend "spi_nor_" to "sr2_bit7_quad_enable". All SPI NOR generic methods should be prepended by "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Merge spansion Quad Enable methodsTudor Ambarus
Merge spansion_no_read_cr_quad_enable() spansion_read_cr_quad_enable() into spi_nor_sr2_bit1_quad_enable(). Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check(). The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1Tudor Ambarus
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Extend the SR Read Back testTudor Ambarus
Test that all the bits from Status Register 1 and Status Register 2 were written correctly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Rework the disabling of block write protectionTudor Ambarus
spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()Tudor Ambarus
Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: fix delayed error detection on HyperFlashSergei Shtylyov
The commit 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") added checking for the status register error bits into chip_good() to only return 1 if these bits are 0s. Unfortunately, this means that polling using chip_good() always reaches a timeout condition when erase or program failure bits are set. Let's fully delegate the task of determining the error conditions to cfi_check_err_status() and make chip_good() only look for the Device Ready/Busy condition. Fixes: 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: only check errors when ready in cfi_check_err_status()Sergei Shtylyov
Cypress S26K{L|S}P{128|256|512}S datasheet says that the error bits in the status register are only valid when the "device ready" bit 7 is set. Add the check for the device ready bit in cfi_check_err_status() as that function isn't always called with this bit set. Fixes: 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: don't free cfi->cfiq in error path of cfi_amdstd_setup()Hou Tao
Else there may be a double-free problem, because cfi->cfiq will be freed by mtd_do_chip_probe() if both the two invocations of check_cmd_set() return failure. Signed-off-by: Hou Tao <houtao1@huawei.com> Reviewed-by: Richard Weinberger <richard@nod.at> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_*: kill useless 'ret' variable initializersSergei Shtylyov
The 'ret' local variables are typically initialized to 0 but this value is often unused, thus we can kill those initializers. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_util: use DIV_ROUND_UP() in cfi_udelay()Sergei Shtylyov
Use DIV_ROUND_UP() in cfi_udelay() instead of open-coding it... Doing this also helpfully gets rid of two complaints from 'scripts/checkpatch.pl --strict': CHECK: spaces preferred around that '+' (ctx:VxV) #29: FILE: drivers/mtd/chips/cfi_util.c:29: + msleep((us+999)/1000); ^ CHECK: spaces preferred around that '/' (ctx:VxV) #29: FILE: drivers/mtd/chips/cfi_util.c:29: + msleep((us+999)/1000); ^ Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Print debug message when the read back test failsTudor Ambarus
Demystify where the EIO error occurs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Check all the bits written, not just the BP onesTudor Ambarus
Check that all the bits written in the write_sr_and_check() method match the status_new received value. Failing to write the other bits is dangerous too, extend the check. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Fix errno on Quad Enable methodsTudor Ambarus
When the Read-Modify-Write-Read-Back Quad Enable methods failed on the Read-Back, they returned -EINVAL. Since this is an I/O error, return -EIO. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Drop spansion_quad_enable()Tudor Ambarus
Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Describe all the Reg OpsTudor Ambarus
Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()Tudor Ambarus
Merge static int spi_nor_write_sr(struct spi_nor *nor, u8 val) static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) into static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) The Status Register can be written with one or two bytes. Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Move the WE and wait calls inside Write SR methodsTudor Ambarus
Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()Tudor Ambarus
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case of errors. The callers didn't check their return value, make them of type void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Rename label as it is no longer genericTudor Ambarus
Rename 'sst_write_err' label to 'out' as it is no longer generic for all the errors in the sst_write() method, and may introduce confusion. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Check for errors after each Register OperationTudor Ambarus
Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Print debug info inside Reg Ops methodsTudor Ambarus
Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Use dev_dbg insted of dev_err for low level infoTudor Ambarus
What most users care about is "my dev is not working properly". All low level information should be discovered when activating the debug traces. Keep error messages just for the following cases: - when the SR/FSR report program or erase fails, or attempts of modifying a protected sector, - when the JEDEC ID is not recognized, - when the resume() call fails, - when the spi_nor_check() fails. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-02mtd: spi-nor: fix silent truncation in spi_nor_read_raw()Sergei Shtylyov
spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: fix silent truncation in spi_nor_read()Sergei Shtylyov
spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e1233bd ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flashMika Westerberg
Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: Print device info in case of errorTudor Ambarus
Print identifying information about struct device. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Constify data to write to the Status RegisterTudor Ambarus
Constify the data to write to the Status Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Fix retlen handling in sst_write()Tudor Ambarus
In case the write of the first byte failed, retlen was incorrectly incremented to *retlen += actual; on the exit path. retlen should be incremented when actual data was written to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop redundant error reports in Reg Ops callersTudor Ambarus
Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()Tudor Ambarus
Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr()Tudor Ambarus
Let the callers pass the pointer to the DMA-able buffer where the value of the Flag Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Caller stops compare the return value of spi_nor_read_fsr() with negative, spi_nor_read_fsr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()Tudor Ambarus
Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>