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Starting with IPA v4.5, IP payload checksum offload is implemented
differently.
Prior to v4.5, the IPA hardware appends an rmnet_map_dl_csum_trailer
structure to each packet if checksum offload is enabled in the
download direction (modem->AP). In the upload direction (AP->modem)
a rmnet_map_ul_csum_header structure is prepended before each sent
packet.
Starting with IPA v4.5, checksum offload is implemented using a
single new rmnet_map_v5_csum_header structure which sits between
the QMAP header and the packet data. The same header structure
is used in both directions.
The new header contains a header type (CSUM_OFFLOAD); a checksum
flag; and a flag indicating whether any other headers follow this
one. The checksum flag indicates whether the hardware should
compute (and insert) the checksum on a sent packet. On a received
packet the checksum flag indicates whether the hardware confirms the
checksum value in the payload is correct.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The backward compatibility register value is a platform-specific
property that is not stored in the platform data. Create a data
field where this can be represented, and get rid ipa_reg_bcr_val().
This register is not present starting with IPA v4.5.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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IPA versions 3.0 and 3.1 support up to 8 resource groups. There is
some interest in supporting these older versions of the hardware, so
update the resource configuration code to program resource limits
for these groups if specified.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Separate the IPA resource-related code into a new source file,
"ipa_resource.c", and matching header file "ipa_resource.h".
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Starting with IPA v4.7, registers related to IPA interrupts are
located at a fixed offset 0x1000 above than the addresses used for
earlier versions. Define and use functions to provide the offset to
use for these registers based on IPA version.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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IPA version 4.9 and later use a different layout of some fields
found in the COMP_CFG register.
Define arbitration_lock_disable_encoded(), and use it to encode a
value into the ATOMIC_FETCHER_ARB_LOCK_DIS field based on the IPA
version.
And define full_flush_rsc_closure_en_encoded() to encode a value
into the FULL_FLUSH_WAIT_RSC_CLOSE_EN field based on the IPA
version.
The values of these fields are neither modified nor extracted by
current code, but this patch makes this possible for all supported
versions.
Fix a mistaken comment above ipa_hardware_config_comp() intended to
describe the purpose for the register.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add and update IPA register definitions. Extend these definitions
to incorporate a fairly small number of new symbols (register
offsets and fields) to support IPA v3.0, v3.1, v3.5, v4.0, v4.1,
v4.7, 4.9, and v4.11, and have the comments reflect when they are
valid. None of the added symbols require changes elsewhere in the
code.
Update rsrc_grp_encoded() to support these other IPA versions.
Add kerneldoc comments for the IPA IRQ numbers and sequencer type.
Fix a few spots where the version check should be less restrictive
(missed by an earlier patch).
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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We only use ipa_aggr_granularity_val() inside "ipa_main.c", so it
doesn't really need to be defined in a header file. It makes some
sense to be grouped with the register definitions, but it is unlike
the other inline functions now defined in "ipa_reg.h". So move it
into "ipa_main.c" where it's used. TIMER_FREQUENCY is used only
by that function, so move that definition as well.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Not all of the bits of the LOCAL_PKT_PROC_CNTXT register are valid.
Until IPA v4.5, there are 17 valid bits (though the bottom three
must be zero). Starting with IPA v4.5, 18 bits are valid.
Introduce proc_cntxt_base_addr_encoded() to encode the base address
for use in the register using only the valid bits.
Shorten the name of the register (omit "_BASE") to avoid the need to
wrap the line in the one place it's used.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Define the ENDP_INIT_NAT register for setting up the NAT
configuration for an endpoint. We aren't using NAT at this
time, so explicitly set the type to BYPASS for all endpoints.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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We only program the sequencer type for TX endpoints. So move the
definition of the sequencer type fields into the TX-specific portion
of the endpoint configuration data. There's no need to maintain
this in the IPA structure; we can extract it from the configuration
data it points to in the one spot it's needed.
We previously specified the sequencer type for RX endpoints with
INVALID values. These are no longer needed, so get rid of them.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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An IPA endpoint has a sequencer that must be configured based on how
the endpoint is to be used. Currently the IPA code programs the
sequencer type by splitting a value into four 4-bit nibbles. Doing
that doesn't really add much value, and regardless, a better way of
splitting the sequencer type is into two halves--the lower byte
describing how normal packet processing is handled, and the next
byte describing information about processing replicas.
So split the sequencer type into two sub-parts: the sequencer type
and the replication sequencer type. Define the values supported for
the "main" sequencer type, and define the values supported for the
replication part separately.
In addition, the sequencer type names are quite verbose, encoding
what the type includes, but also what it *excludes*. Rename the
sequencer types in a way that mainly describes the number of passes
that a packet takes through the IPA processing pipeline, and how
many of those passes end by supplying the processed packet to the
microprocessor.
The result expands the supported types beyond what is required for
now, but simplifies the way these are defined.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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It's possible that the length passed to ipa_header_size_encoded()
is larger than what can be represented by the HDR_LEN field alone
(starting with IPA v4.5). If we attempted that, u32_encode_bits()
would trigger a build-time error.
Avoid this problem by masking off high-order bits of the value
encoded as the lower portion of the header length.
The same sort of problem exists in ipa_metadata_offset_encoded(),
so implement the same fix there.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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IPA v4.5 introduces a new unified timer architecture driven on the
19.2 MHz SoC crystal oscillator (XO). It is independent of the IPA
core clock and avoids some duplication.
Lower-resolution time stamps are derived from this by using only the
high-order bits of the 19.2 MHz Qtime clock. And timers are derived
from this based on "pulse generators" configured to fire at a fixed
rate based on the Qtime clock.
This patch introduces ipa_qtime_config(), which configures the Qtime
mechanism for use. It also adds to the IPA register definitions
related to timers and time stamping.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Update the IPA code to make use of the updated IPA v4.5 register
definitions. Generally what this patch does is, if IPA v4.5
hardware is in use:
- Ensure new registers or fields in IPA v4.5 are updated where
required
- Ensure registers or fields not supported in IPA v4.5 are not
examined when read, or are set to 0 when written
It does this while preserving the existing functionality for IPA
versions lower than v4.5.
The values to program for QSB_MAX_READS and QSB_MAX_WRITES and the
source and destination resource counts are updated to be correct for
all versions through v4.5 as well.
Note that IPA_RESOURCE_GROUP_SRC_MAX and IPA_RESOURCE_GROUP_DST_MAX
already reflect that 5 is an acceptable number of resources (which
IPA v4.5 implements).
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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IPA v4.5 adds a few fields to the endpoint header and extended
header configuration registers that represent new high-order bits
for certain offsets and sizes. Add code to incorporate these upper
bits into the registers for IPA v4.5.
This includes creating ipa_header_size_encoded(), which handles
encoding the metadata offset field for use in the ENDP_INIT_HDR
register in a way appropriate for the hardware version. This and
ipa_metadata_offset_encoded() ensure the mask argument passed to
u32_encode_bits() is constant.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Update "ipa_reg.h" so that register definitions support IPA hardware
version 4.5, in addition to versions 3.5.1 through v4.2. Most of
the register definitions are the same, but in some cases fields are
added, changed, or eliminated.
Updates for a few IPA v4.5 registers are more complex, and adding
those definition will be deferred to separate patches. This patch
only updates the register offset and field definitions, and adds
informational comments.
The only code change avoids accessing the backward compatibility
register for IPA version 4.5 in ipa_hardware_config(). Other IPA
v4.5-specific code changes will come later.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Some last cleanups for the existing IPA register definitions:
- Remove the definition of IPA_REG_ENABLED_PIPES_OFFSET, because
it is not used.
- Use "IPA_" instead of "BAM_" as the prefix on fields associated
with the FLAVOR_0 register. We use GSI (not BAM), but the
fields apply to both GSI and BAM.
- Get rid of the definition of IPA_CS_RSVD; it is never used.
- Add two missing field mask definitions for the INIT_DEAGGR
endpoint register.
- Eliminate a few of the defined sequencer types, because they
are unused. We can add them back when needed.
- Add a field mask to indicate which bit causes an interrupt on
the microcontroller.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Move the definition of the ipa_irq_id enumerated type out of
"ipa_interrupt.h" and into "ipa_reg.h", and flesh out its set of
defined values. Each interrupt id indicates a particular type of
IPA interrupt that can be signaled. Their numeric values define bit
positions in the IPA_IRQ_* registers, so should their definitions
should accompany the definition of those register offsets.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Move a few things around in "ipa_reg.h":
- Move the definition of ipa_reg_state_aggr_active_offset() down
a bit in the file so definitions are ordered by offset (for
the lowest supported IPA version) like all other definitions.
- Move the definition TIMER_FREQUENCY to be immediately above
the definition of ipa_aggr_granularity_val() where it's used.
- Move each register field value enumerated type definition to
immediately follow the definitions of the register and field
it is associated with.
No code functionality is modified by this patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Revise or add comments in "ipa_reg.h" for to provide more
information, and to improve clarity and consistency.
- Always provide a comment to define when a register or field is
supported (or not) for certain versions of IPA hardware.
- Try to be specific about *which* or *how many* definitions
a comment refers to.
- Move comments stating that ipa->available defines the valid
bits in various registers *above* the register offset
definition, to avoid some checkpatch.pl warnings.
No code is changed by this patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Consistently define numeric values for enumerated type members using
hexidecimal (rather than decimal) format values. Align the values
assigned in the same column in each file.
Only assign values where they really matter, for example don't
assign IPA_ENDPOINT_AP_MODEM_TX the value 0.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The backward compatibility register field masks are defined using
single-bit masks defined with BIT(x) rather than GENMASK(x, x).
Change this one set of definitions to follow the GENMASK() pattern
used everywhere else. Add a few missing field definitions for this
register as well.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Several IPA register field masks are defined without the "_FMASK"
suffix naming convention. Rename these, so all field masks are
consistently named.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Rename two suspend IRQ registers so they follow the IPA_REG_IRQ_xxx
naming convention used elsewhere.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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For IPA v3.5.1, the IPA filter/routing hash enable register actually
does exist, but it is at offset 0x8c into the IPA register space.
For newer versions of IPA it is at offset 0x148.
Define a new inline function ipa_reg_filt_rout_hash_en_offset() to
return the appropriate value for a given version of IPA hardware.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The IPA filter/routing hash enable register and filter/routing hash
flush register each have four single-bit fields representing the
four hashed tables to be enabled or flushed. The field positions
are identical, so just use a single set of field masks to represent
the fields for both registers.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The number of resource groups supported by the hardware can be
different for source and destination resources. Determine the
number supported for each using separate functions. Make the
functions inline end move their definitions into "ipa_reg.h",
because they determine whether certain register definitions are
valid. Pass just the IPA hardware version as argument.
IPA_RESOURCE_GROUP_COUNT represents the maximum number of resource
groups the driver supports for any hardware version. Change that
symbol to be two separate constants, one for source and the other
for destination resource groups. Rename them to end with "_MAX"
rather than "_COUNT", to reflect their true purpose.
Tested-by: Sujit Kautkar <sujitka@chromium.org>
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The mask for the RSRC_GRP field in the INIT_RSRC_GRP endpoint
initialization register is incorrectly defined for IPA v4.2 (where
it is only one bit wide). So we need to fix this.
The fix is not straightforward, however. Field masks are passed to
functions like u32_encode_bits(), and for that they must be constant.
To address this, we define a new inline function that returns the
*encoded* value to use for a given RSRC_GRP field, which depends on
the IPA version. The caller can then use something like this, to
assign a given endpoint resource id 1:
u32 offset = IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(endpoint_id);
u32 val = rsrc_grp_encoded(ipa->version, 1);
iowrite32(val, ipa->reg_virt + offset);
The next patch requires this fix.
Tested-by: Sujit Kautkar <sujitka@chromium.org>
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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In ipa_uc_response_hdlr() a comment uses the wrong function name
when it describes where a clock reference is taken. Fix this.
Also fix the comment in ipa_uc_response_hdlr() to correctly refer to
ipa_uc_setup(), which is where the clock reference described here is
taken.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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A handful of registers are valid only for RX endpoints, and some
others are valid only for TX endpoints. For these endpoints, add
a comment above their defined offset macro that indicates the
endpoints to which they apply.
Extend the endpoint parameter naming convention as well, to make
these constraints more explicit.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The timer used for aggregation makes use of an internal 32 KHz clock.
The granularity of the timer is programmed by a field whose value is
computed by ipa_aggr_granularity_val(). Redefine the way that value
is computed by using a new TIMER_FREQUENCY constant representing the
underlying clock frequency.
Add two BUILD_BUG_ON() calls to ensure the value used is valid.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The upper two nibbles of the sequencer type were not used for
SDM845, and were assumed to be 0. But for SC7180 they are used, and
so they must be programmed by ipa_endpoint_init_seq(). Fix this bug.
IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP doesn't have a descriptive
comment, so add one.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch includes three source files that represent some basic "main
program" code for the IPA driver. They are:
- "ipa.h" defines the top-level IPA structure which represents an IPA
device throughout the code.
- "ipa_main.c" contains the platform driver probe function, along with
some general code used during initialization.
- "ipa_reg.h" defines the offsets of the 32-bit registers used for the
IPA device, along with masks that define the position and width of
fields within these registers.
- "version.h" defines some symbolic IPA version numbers.
Each file includes some documentation that provides a little more
overview of how the code is organized and used.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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