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path: root/drivers/pci/controller/pci-mvebu.c
AgeCommit message (Collapse)Author
24 hoursimplement slot capabilities (SSPL)Russell King
24 hoursmvebu/clearfog pcie updatesRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2023-10-10PCI: mvebu: Use FIELD_PREP() with Link WidthIlpo Järvinen
mvebu_pcie_setup_hw() setups the Maximum Link Width field in the Link Capabilities registers using an open-coded variant of FIELD_PREP() with a literal in shift. Improve readability by using FIELD_PREP(PCI_EXP_LNKCAP_MLW, ...). Link: https://lore.kernel.org/r/20230919125648.1920-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2023-08-25PCI: mvebu: Remove unused busn memberPali Rohár
The busn member of struct mvebu_pcie is unused, so drop it. Link: https://lore.kernel.org/r/20220905192310.22786-5-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-06-24PCI: mvebu: Convert to platform remove callback returning voidUwe Kleine-König
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Link: https://lore.kernel.org/linux-pci/20230321193208.366561-13-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2022-12-10Merge branch 'pci/kbuild'Bjorn Helgaas
- Remove unnecessary <linux/of_irq.h> includes (Bjorn Helgaas) * pci/kbuild: PCI: Drop of_match_ptr() to avoid unused variables PCI: Remove unnecessary <linux/of_irq.h> includes PCI: xgene-msi: Include <linux/irqdomain.h> explicitly PCI: mvebu: Include <linux/irqdomain.h> explicitly PCI: microchip: Include <linux/irqdomain.h> explicitly PCI: altera-msi: Include <linux/irqdomain.h> explicitly # Conflicts: # drivers/pci/controller/pci-mvebu.c
2022-12-07PCI: mvebu: Switch to using gpiod APIDmitry Torokhov
Switch the driver away from legacy gpio/of_gpio API to gpiod API, and remove use of of_get_named_gpio_flags() which I want to make private to gpiolib. Link: https://lore.kernel.org/r/Y5EAft42YiT66mVj@google.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-11-10PCI: mvebu: Include <linux/irqdomain.h> explicitlyBjorn Helgaas
pci-mvebu.c uses irq_domain_add_linear() and related interfaces but relies on <linux/irqdomain.h> but doesn't include it directly; it relies on the fact that <linux/of_irq.h> includes it. Include <linux/irqdomain.h> directly to remove this implicit dependency. Link: https://lore.kernel.org/r/20221031153954.1163623-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2022-10-05Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas
- Fix endianness of emulated bridge iolimitupper, iobaseupper, memlimit and membase members (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Fix endianness when accessing PCI emul bridge members
2022-08-25PCI: pci-bridge-emul: Set position of PCI capabilities to real HW valuePali Rohár
mvebu and aardvark HW have PCIe capabilities on different offset in PCI config space. Extend pci-bridge-emul.c code to allow setting custom driver custom value where PCIe capabilities starts. With this change PCIe capabilities of both drivers are reported at the same location as where they are reported by U-Boot - in their real HW offset. Link: https://lore.kernel.org/r/20220824112124.21675-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-08-23PCI: mvebu: Fix endianness when accessing PCI emul bridge membersPali Rohár
PCI emul bridge members iolimitupper, iobaseupper, memlimit and membase are of type __le16, so correctly access these members using le16_to_cpu() macros. Link: https://lore.kernel.org/r/20220812141115.24082-1-pali@kernel.org Fixes: e7a01876729c ("PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-07-27PCI: Convert to new *_PM_OPS macrosBjorn Helgaas
Replace SET_*_PM_OPS with *_PM_OPS, which which have the advantage that the compiler always sees the PM callbacks as referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to avoid "defined but not used" warnings. See 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). Link: https://lore.kernel.org/r/20220719215108.1583108-1-helgaas@kernel.org Tested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pali Rohár <pali@kernel.org> # pci-mvebu.c Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2022-04-25PCI: mvebu: Add support for sending Set_Slot_Power_Limit messagePali Rohár
If DT supplies the 'slot-power-limit-milliwatt' property, program the value in the Slot Power Limit in the Slot Capabilities register and program the Root Port to send a Set_Slot_Power_Limit Message when the Link transitions to DL_Up. Link: https://lore.kernel.org/r/20220412094946.27069-5-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-03-25Merge tag 'pci-v5.18-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Move the VGA arbiter from drivers/gpu to drivers/pci because it's PCI-specific, not GPU-specific (Bjorn Helgaas) - Select the default VGA device consistently whether it's enumerated before or after VGA arbiter init, which fixes arches that enumerate PCI devices late (Huacai Chen) Resource management: - Support BAR sizes up to 8TB (Dongdong Liu) PCIe native device hotplug: - Fix "Command Completed" tracking to avoid spurious timouts when powering off empty slots (Liguang Zhang) - Quirk Qualcomm devices that don't implement Command Completed correctly, again to avoid spurious timeouts (Manivannan Sadhasivam) Peer-to-peer DMA: - Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist (Michael J. Ruhl) APM X-Gene PCIe controller driver: - Revert generic DT parsing changes that broke some machines in the field (Marc Zyngier) Freescale i.MX6 PCIe controller driver: - Allow controller probe to succeed even when no devices currently present to allow hot-add later (Fabio Estevam) - Enable power management on i.MX6QP (Richard Zhu) - Assert CLKREQ# on i.MX8MM so enumeration doesn't hang when no device is connected (Richard Zhu) Marvell Aardvark PCIe controller driver: - Fix MSI and MSI-X support (Marek Behún, Pali Rohár) - Add support for ERR and PME interrupts (Pali Rohár) Marvell MVEBU PCIe controller driver: - Add DT binding and support for "num-lanes" (Pali Rohár) - Add support for INTx interrupts (Pali Rohár) Microsoft Hyper-V host bridge driver: - Avoid unnecessary hypercalls when unmasking IRQs on ARM64 (Boqun Feng) Qualcomm PCIe controller driver: - Add SM8450 DT binding and driver support (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Help the controller get to the L1 state since the hardware can't do it on its own (Marek Vasut) - Return PCI_ERROR_RESPONSE (~0) for reads that fail on PCIe (Marek Vasut) SiFive FU740 PCIe controller driver: - Drop redundant '-gpios' from DT GPIO lookup (Ben Dooks) - Force 2.5GT/s for initial device probe (Ben Dooks) Socionext UniPhier Pro5 controller driver: - Add NX1 DT binding and driver support (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Restore MSI configuration so MSI works after resume (Jisheng Zhang)" * tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (94 commits) x86/PCI: Add #includes to asm/pci_x86.h PCI: ibmphp: Remove unused assignments PCI: cpqphp: Remove unused assignments PCI: fu740: Remove unused assignments PCI: kirin: Remove unused assignments PCI: Remove unused assignments PCI: Declare pci_filp_private only when HAVE_PCI_MMAP PCI: Avoid broken MSI on SB600 USB devices PCI: fu740: Force 2.5GT/s for initial device probe PCI: xgene: Revert "PCI: xgene: Fix IB window setup" PCI: xgene: Revert "PCI: xgene: Use inbound resources for setup" PCI: imx6: Assert i.MX8MM CLKREQ# even if no device present PCI: imx6: Invoke the PHY exit function after PHY power off PCI: rcar: Use PCI_SET_ERROR_RESPONSE after read which triggered an exception PCI: rcar: Finish transition to L1 state in rcar_pcie_config_access() PCI: dwc: Restore MSI Receiver mask during resume PCI: fu740: Drop redundant '-gpios' from DT GPIO lookup PCI/VGA: Replace full MIT license text with SPDX identifier PCI/VGA: Use unsigned format string to print lock counts PCI/VGA: Log bridge control messages when adding devices ...
2022-03-22Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas
- Add Pali Rohár as pci-mvebu.c maintainer (Pali Rohár) - Make struct pci_bridge_emul_ops const (Pali Rohár) - Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD since it doesn't apply to BARs (Pali Rohár) - Add new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD for bridges that don't support IO forwarding (Pali Rohár) - Add Kconfig help text for CONFIG_PCI_MVEBU (Pali Rohár) - Remove duplicate nports assignment (Pali Rohár) - Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported (Pali Rohár) - Initialize vendor, device and revision of emulated bridge (Pali Rohár) - Fix Data Link Layer Link Active reporting on emulated bridge (Pali Rohár) - Rearrange tests in bridge emulation for easier maintenance (Russell King) - Add emulated bridge support for PCIe extended capabilities (Russell King) - Add emulated bridge support for bridge Subsystem Vendor ID capability (Pali Rohár) - Configure Maximum Link Width based on DT "num-lanes" property (Pali Rohár) - Emulate bridge Subsystem Vendor ID capability (Pali Rohár) - Emulate AER Capability (Pali Rohár) - Use PCI core bridge->ops and bridge->child_ops to separate config accesses to Root Port vs downstream devices (Pali Rohár) - Unmask all INTx interrupts; they're reported via a single shared GIC source (Pali Rohár) - Add INTx support (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Implement support for legacy INTx interrupts PCI: mvebu: Fix macro names and comments about legacy interrupts dt-bindings: PCI: mvebu: Update information about intx interrupts PCI: mvebu: Use child_ops API PCI: mvebu: Add support for Advanced Error Reporting registers on emulated bridge PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge PCI: mvebu: Correctly configure x1/x4 mode dt-bindings: PCI: mvebu: Add num-lanes property PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability PCI: pci-bridge-emul: Add support for PCIe extended capabilities PCI: pci-bridge-emul: Re-arrange register tests PCI: mvebu: Fix reporting Data Link Layer Link Active on emulated bridge PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge PCI: mvebu: Properly initialize vendor, device and revision of emulated bridge PCI: mvebu: Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported PCI: mvebu: Remove duplicate nports assignment PCI: mvebu: Add help string for CONFIG_PCI_MVEBU option PCI: pci-bridge-emul: Add support for new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD PCI: pci-bridge-emul: Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD PCI: pci-bridge-emul: Make struct pci_bridge_emul_ops as const MAINTAINERS: Add Pali Rohár as pci-mvebu.c maintainer
2022-02-22PCI: mvebu: Implement support for legacy INTx interruptsPali Rohár
This adds support for legacy INTx interrupts received from other PCIe devices and which are reported by a new INTx irq chip. With this change, kernel can distinguish between INTA, INTB, INTC and INTD interrupts. Note that for this support, device tree files has to be properly adjusted to provide "interrupts" or "interrupts-extended" property with intx interrupt source, "interrupt-names" property with "intx" string and also 'interrupt-controller' subnode must be defined. If device tree files do not provide these nodes then driver would work as before. Link: https://lore.kernel.org/r/20220222155030.988-12-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-22PCI: mvebu: Fix macro names and comments about legacy interruptsPali Rohár
Register 0x1910 unmasks interrupts and legacy INTx interrupts are unmasked because driver does not support individual masking yet. Link: https://lore.kernel.org/r/20220222155030.988-11-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-22PCI: mvebu: Use child_ops APIPali Rohár
Split struct pci_ops between ops and child_ops. Member ops is used for accessing PCIe Root Ports via pci-bridge-emul.c driver and child_ops for accessing real PCIe cards. There is no need to mix these two struct pci_ops into one as PCI core code already provides separate callbacks via bridge->ops and bridge->child_ops. Link: https://lore.kernel.org/r/20220222155030.988-9-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-22PCI: mvebu: Add support for Advanced Error Reporting registers on emulated ↵Pali Rohár
bridge AER registers start at mvebu offset 0x0100. Registers PCI_ERR_ROOT_COMMAND, PCI_ERR_ROOT_STATUS and PCI_ERR_ROOT_ERR_SRC are not supported on pre-XP hardware and returns zeros. Note that AER interrupt is not supported yet as mvebu emulated bridge does not implement interrupts support at all yet. Also remove custom macro PCIE_HEADER_LOG_4_OFF as it is unused and correctly this register should be referenced via standard macros with offset, e.g. as: PCIE_CAP_PCIERR_OFF + PCI_ERR_HEADER_LOG + 4. Link: https://lore.kernel.org/r/20220222155030.988-8-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-22PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridgePali Rohár
Register with Subsystem Device/Vendor ID is at offset 0x2c. Export is via emulated bridge. After this change Subsystem ID is visible in lspci output at line: Capabilities: [40] Subsystem Link: https://lore.kernel.org/r/20220222155030.988-7-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-22PCI: mvebu: Correctly configure x1/x4 modePali Rohár
If x1/x4 mode is not set correctly then link with endpoint card is not established. Use DTS property 'num-lanes' to deteriminate x1/x4 mode. Link: https://lore.kernel.org/r/20220222155030.988-6-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-02-17PCI: Add defines for normal and subtractive PCI bridgesPali Rohár
Add these PCI class codes to pci_ids.h: PCI_CLASS_BRIDGE_PCI_NORMAL PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE Use these defines in all kernel code for describing PCI class codes for normal and subtractive PCI bridges. [bhelgaas: similar change in pci-mvebu.c] Link: https://lore.kernel.org/r/20220214114109.26809-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-02-14PCI: mvebu: Fix device enumeration regressionPali Rohár
Jan reported that on Turris Omnia (Armada 385), no PCIe devices were detected after upgrading from v5.16.1 to v5.16.3 and identified the cause as the backport of 91a8d79fc797 ("PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge"), which appeared in v5.17-rc1. 91a8d79fc797 was incorrectly applied from mailing list patch [1] to the linux git repository [2] probably due to resolving merge conflicts incorrectly. Fix it now. [1] https://lore.kernel.org/r/20211125124605.25915-12-pali@kernel.org [2] https://git.kernel.org/linus/91a8d79fc797 [bhelgaas: commit log] BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215540 Fixes: 91a8d79fc797 ("PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge") Link: https://lore.kernel.org/r/20220214110228.25825-1-pali@kernel.org Link: https://lore.kernel.org/r/20220127234917.GA150851@bhelgaas Reported-by: Jan Palus <jpalus@fastmail.com> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-02-03PCI: mvebu: Fix reporting Data Link Layer Link Active on emulated bridgePali Rohár
Add support for reporting PCI_EXP_LNKSTA_DLLLA bit in Link Control register on emulated bridge via PCIE_STAT_OFF reg. Function mvebu_pcie_link_up() already parses this register and returns if Data Link is Active or not. Also correctly indicate DLLLA capability via PCI_EXP_LNKCAP_DLLLARC bit in Link Control Capability register which is required for reporting DLLLA bit. Link: https://lore.kernel.org/r/20220104153529.31647-12-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridgePali Rohár
Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be hardwired to zero but mvebu hw allows to change it. Link: https://lore.kernel.org/r/20220104153529.31647-11-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridgePali Rohár
Reason for clearing this bit is because mvebu hw returns incorrectly this bit set to 1. Link: https://lore.kernel.org/r/20220104153529.31647-10-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: mvebu: Properly initialize vendor, device and revision of emulated bridgePali Rohár
With this change also PCI vendor id is read from mvebu registers. Link: https://lore.kernel.org/r/20220104153529.31647-9-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: mvebu: Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupportedPali Rohár
This will make PCI bridge to return zeros when accessing IO base and limit registers, as required by PCIe base specification. This allows to remove adhoc checks around mvebu_pcie_handle_iobase_change() function for unsupported IO ranges. PCI_BRIDGE_EMUL_NO_IO_FORWARD ensures that there will be no non-zeros write to IO registers when IO is not supported. Link: https://lore.kernel.org/r/20220104153529.31647-8-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: mvebu: Remove duplicate nports assignmentPali Rohár
Member pcie->nports is initialized to correct value before the previous for-loop. There is not need to initialize it more times. Link: https://lore.kernel.org/r/20220104153529.31647-7-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2022-02-03PCI: pci-bridge-emul: Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to ↵Pali Rohár
PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD This flag describe whether PCI bridge supports forwarding of prefetchable memory requests in given range between primary and secondary buses. It does not specify if bridge has support for prefetchable memory BAR (moreover this pci-bridge-emul.c driver does not provide support for BARs). So change name of this flag to be less misleading and add comment. Link: https://lore.kernel.org/r/20220104153529.31647-4-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-03PCI: pci-bridge-emul: Make struct pci_bridge_emul_ops as constPali Rohár
It is read-only constant structure, so properly mark it with const keyword. Link: https://lore.kernel.org/r/20220104153529.31647-3-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2022-01-13Merge branch 'pci/errors'Bjorn Helgaas
- Add PCI_ERROR_RESPONSE and related definitions for signaling and checking for transaction errors on PCI (Naveen Naidu) - Fabricate PCI_ERROR_RESPONSE data (~0) in config read wrappers, instead of in host controller drivers, when transactions fail on PCI (Naveen Naidu) - Use PCI_POSSIBLE_ERROR() to check for possible failure of config reads (Naveen Naidu) * pci/errors: PCI: xgene: Use PCI_ERROR_RESPONSE to identify config read errors PCI: hv: Use PCI_ERROR_RESPONSE to identify config read errors PCI: keystone: Use PCI_ERROR_RESPONSE to identify config read errors PCI: Use PCI_ERROR_RESPONSE to identify config read errors PCI: cpqphp: Use PCI_POSSIBLE_ERROR() to check config reads PCI/PME: Use PCI_POSSIBLE_ERROR() to check config reads PCI/DPC: Use PCI_POSSIBLE_ERROR() to check config reads PCI: pciehp: Use PCI_POSSIBLE_ERROR() to check config reads PCI: vmd: Use PCI_POSSIBLE_ERROR() to check config reads PCI/ERR: Use PCI_POSSIBLE_ERROR() to check config reads PCI: rockchip-host: Drop error data fabrication when config read fails PCI: rcar-host: Drop error data fabrication when config read fails PCI: altera: Drop error data fabrication when config read fails PCI: mvebu: Drop error data fabrication when config read fails PCI: aardvark: Drop error data fabrication when config read fails PCI: kirin: Drop error data fabrication when config read fails PCI: histb: Drop error data fabrication when config read fails PCI: exynos: Drop error data fabrication when config read fails PCI: mediatek: Drop error data fabrication when config read fails PCI: iproc: Drop error data fabrication when config read fails PCI: thunder: Drop error data fabrication when config read fails PCI: Drop error data fabrication when config read fails PCI: Use PCI_SET_ERROR_RESPONSE() for disconnected devices PCI: Set error response data when config read fails PCI: Add PCI_ERROR_RESPONSE and related definitions
2022-01-13Merge branch 'remotes/lorenzo/pci/bridge-emul'Bjorn Helgaas
- Make emulated ROM BAR read-only by default (Pali Rohár) - Make some emulated legacy PCI bits read-only for PCIe devices (Pali Rohár) - Update reserved bits in emulated PCIe Capability (Pali Rohár) - Allow drivers to emulate different PCIe Capability versions (Pali Rohár) - Set emulated Capabilities List bit for all PCIe devices, since they must have at least a PCIe Capability (Pali Rohár) * remotes/lorenzo/pci/bridge-emul: PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device PCI: pci-bridge-emul: Correctly set PCIe capabilities PCI: pci-bridge-emul: Fix definitions of reserved bits PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
2022-01-06PCI: mvebu: Add support for compiling driver as modulePali Rohár
Now when driver uses devm_pci_remap_iospace() function, it is possible implement ->remove() callback for unbinding device from driver. Implement mvebu_pcie_remove() callback with proper cleanup phase, drop driver's suppress_bind_attrs flag and switch type of CONFIG_PCI_MVEBU option from bool to tristate. This allows to compile pci-mvebu.c driver as loadable module pci-mvebu.ko with ability to unload it. Link: https://lore.kernel.org/r/20211126144307.7568-3-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on ↵Pali Rohár
emulated bridge Armada XP and new hardware supports access to DEVCAP2, DEVCTL2 and LNKCTL2 configuration registers of PCIe core via PCIE_CAP_PCIEXP. So export them via emulated software root bridge. Pre-XP hardware does not support these registers and returns zeros. Link: https://lore.kernel.org/r/20211125124605.25915-16-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridgePali Rohár
PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) is read-only and can be cleared only by writing 0b to the Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). Link: https://lore.kernel.org/r/20211125124605.25915-15-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridgePali Rohár
Comment in Armada 370 functional specification is misleading. PCI_EXP_DEVCTL_*RE bits are supported and configures receiving of error interrupts. Link: https://lore.kernel.org/r/20211125124605.25915-14-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridgePali Rohár
Hardware supports PCIe Hot Reset via PCIE_CTRL_OFF register. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this change the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Link: https://lore.kernel.org/r/20211125124605.25915-13-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridgePali Rohár
It looks like that mvebu PCIe controller has for each PCIe link fully independent PCIe host bridge and so every PCIe Root Port is isolated not only on its own bus but also isolated from each others. But in past device tree structure was defined to put all PCIe Root Ports (as PCI Bridge devices) into one root bus 0 and this bus is emulated by pci-mvebu.c driver. Probably reason for this decision was incorrect understanding of PCIe topology of these Armada SoCs and also reason of misunderstanding how is PCIe controller generating Type 0 and Type 1 config requests (it is fully different compared to other drivers). Probably incorrect setup leaded to very surprised things like having PCIe Root Port (PCI Bridge device, with even incorrect Device Class set to Memory Controller) and the PCIe device behind the Root Port on the same PCI bus, which obviously was needed to somehow hack (as these two devices cannot be in reality on the same bus). Properly set mvebu local bus number and mvebu local device number based on PCI Bridge secondary bus number configuration. Also correctly report configured secondary bus number in config space. And explain in driver comment why this setup is correct. Link: https://lore.kernel.org/r/20211125124605.25915-12-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Set PCI Bridge Class Code to PCI BridgePali Rohár
The default value of Class Code of this bridge corresponds to a Memory controller, though. This is probably relict from the past when old Marvell/Galileo PCI-based controllers were used as standalone PCI device for connecting SDRAM or workaround for PCs with broken BIOS. Details are in commit 36de23a4c5f0 ("MIPS: Cobalt: Explain GT64111 early PCI fixup"). Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Link: https://lore.kernel.org/r/20211125124605.25915-11-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Setup PCIe controller to Root Complex modePali Rohár
This driver operates only in Root Complex mode, so ensure that hardware is properly configured in Root Complex mode. Link: https://lore.kernel.org/r/20211125124605.25915-10-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE ↵Pali Rohár
registers Properly propagate failure from mvebu_pcie_add_windows() function back to the caller mvebu_pci_bridge_emul_base_conf_write() and correctly updates PCI_IO_BASE, PCI_MEM_BASE and PCI_IO_BASE_UPPER16 registers on error. On error set base value higher than limit value which indicates that address range is disabled. When IO is unsupported then let IO registers zeroed as required by PCIe base specification. Link: https://lore.kernel.org/r/20211125124605.25915-9-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Do not modify PCI IO type bits in conf_writePali Rohár
PCI IO type bits are already initialized in mvebu_pci_bridge_emul_init() function and only when IO support is enabled. These type bits are read-only and pci-bridge-emul.c code already does not allow to modify them from upper layers. When IO support is disabled then all IO registers should be read-only and return zeros. Therefore do not modify PCI IO type bits in mvebu_pci_bridge_emul_base_conf_write() callback. Link: https://lore.kernel.org/r/20211125124605.25915-8-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridgePali Rohár
According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early beginning of driver initialization. Also remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of PCI Bridge via emulated PCI_COMMAND on emulated bridge. Adjust existing functions mvebu_pcie_handle_iobase_change() and mvebu_pcie_handle_membase_change() to handle PCI_IO_BASE and PCI_MEM_BASE registers correctly even when bus mastering on emulated bridge is disabled. Link: https://lore.kernel.org/r/20211125124605.25915-7-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Disallow mapping interrupts on emulated bridgesPali Rohár
Interrupt support on mvebu emulated bridges is not implemented yet. So properly indicate return value to callers that they cannot request interrupts from emulated bridge. Link: https://lore.kernel.org/r/20211125124605.25915-6-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Handle invalid size of read config requestPali Rohár
Function mvebu_pcie_hw_rd_conf() does not handle invalid size. So correctly set read value to all-ones and return appropriate error return value PCIBIOS_BAD_REGISTER_NUMBER like in mvebu_pcie_hw_wr_conf() function. Link: https://lore.kernel.org/r/20211125124605.25915-5-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Check that PCI bridge specified in DT has function number zeroPali Rohár
Driver cannot handle PCI bridges at non-zero function address. So add appropriate check. Currently all in-tree kernel DTS files set PCI bridge function to zero. Link: https://lore.kernel.org/r/20211125124605.25915-4-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Check for errors from pci_bridge_emul_init() callPali Rohár
Function pci_bridge_emul_init() may fail so correctly check for errors. Link: https://lore.kernel.org/r/20211125124605.25915-3-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Check for valid portsPali Rohár
Some mvebu ports do not have to be initialized. So skip these uninitialized mvebu ports in every port iteration function to prevent access to unmapped memory or dereferencing NULL pointers. Uninitialized mvebu port has base address set to NULL. Link: https://lore.kernel.org/r/20211125124605.25915-2-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-06PCI: pci-bridge-emul: Correctly set PCIe capabilitiesPali Rohár
Older mvebu hardware provides PCIe Capability structure only in version 1. New mvebu and aardvark hardware provides it in version 2. So do not force version to 2 in pci_bridge_emul_init() and rather allow drivers to set correct version. Drivers need to set version in pcie_conf.cap field without overwriting PCI_CAP_LIST_ID register. Both drivers (mvebu and aardvark) do not provide slot support yet, so do not set PCI_EXP_FLAGS_SLOT flag. Link: https://lore.kernel.org/r/20211124155944.1290-6-pali@kernel.org Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org
generated by cgit (git 2.34.1) at 2024-05-01 07:47:40 +0000