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path: root/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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2023-04-10phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tblDmitry Baryshkov
The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX table is empty, so we can drop it completely. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230331151250.4049-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-04-10phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanesDmitry Baryshkov
All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of lanes to 2. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Cc: stable@vger.kernel.org # 5.15 Sgned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230331151250.4049-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: qcom-qmp: Add support for SDX65 QMP PCIe PHYRohit Agarwal
The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: qcom-qmp-pcie: Add RC init sequence for SDX55Manivannan Sadhasivam
Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55Manivannan Sadhasivam
In preparation for adding RC support, let's split out the EP related init sequence so that the common sequence could be reused by RC as well. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-12-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEsAbel Vesa
Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHYDmitry Baryshkov
The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove possible confusion. Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212138.421583-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp: move type-specific headers to particular driverDmitry Baryshkov
Remove QMP PHY type-specific headers inclusion from the common header and move them to the specific PHY drivers to cleanup the namespaces used by different drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-14-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-pcie: rename regs layout arraysDmitry Baryshkov
Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-pcie: rework regs layout arraysDmitry Baryshkov
Use symbolic names for the values inside reg layout arrays. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-pcie: add support for sm8350 platformDmitry Baryshkov
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm SM8350 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221118233242.2904088-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tablesDmitry Baryshkov
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Rename generic tables to remove x1 suffix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221118233242.2904088-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tablesDmitry Baryshkov
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Split these tables to be used by SM8350 config. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221118233242.2904088-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-24phy: qcom-qmp-pcie: drop redundant clock allocationJohan Hovold
Since the QMP driver split, there is no reason to allocate the fixed-rate pipe clock structure separately from the driver data. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221111094239.11547-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-24phy: qcom-qmp: drop unused type headerJohan Hovold
The PHY type defines are no longer used in the PCIe, UFS and USB QMP drivers so drop the corresponding include. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221111094239.11547-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register namesManivannan Sadhasivam
sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS registers of QMP PHY v5.20. So use the v5.20 specific register names. Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to PCS_EQ_CONFIG{4/5}. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: Fix high latency with 4x2 PHY when ASPM is enabledManivannan Sadhasivam
The PCIe QMP 4x2 RC PHY generates high latency when ASPM is enabled. This seem to be fixed by clearing the QPHY_V5_20_PCS_PCIE_PRESET_P10_POST register of the pcs_misc register space. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20221102081835.41892-1-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: split pcs_misc init cfg for ipq8074 pcs tableChristian Marangi
Commit af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3") reworked the pcs regs values and removed the 0x400 offset for each pcs_misc regs. This change caused the malfunction of ipq8074 downstream since it still has the legacy pcs table where pcs_misc are not placed on a different table and instead put together assuming the offset of 0x400 for the related pcs_misc regs. Split pcs_misc init cfg from the ipq8074 pcs init table to be handled correctly to prepare for actual support for gen3 pcie for ipq8074. Fixes: af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3") Reported-by: Robert Marko <robimarko@gmail.com> Tested-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20221103212125.17156-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYsJohan Hovold
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as PCIe2A and PCIe2B). Add support for fetching the 4-lane configuration from the TCSR and programming the lane registers of the second port when in 4-lane mode. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-17-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: add support for sc8280xpJohan Hovold
Add support for the single and dual-lane PHYs found on SC8280XP. Note that the SC8280XP binding does not try to describe every register subregion and instead the driver holds the corresponding offsets. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-16-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: add support for pipediv2 clockJohan Hovold
Some QMP PHYs have a second fixed-divider pipe clock that needs to be enabled along with the pipe clock. Add support for an optional "pipediv2" clock. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-15-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: fix initialisation resetJohan Hovold
Add the missing delay after asserting reset. This is specifically needed for the reset to have any effect on SC8280XP. The vendor driver uses a 1 ms delay, but that seems a bit excessive. Instead use a 200 us delay which appears to be more than enough and also matches the UFS reset delay added by commit 870b1279c7a0 ("scsi: ufs-qcom: Add reset control support for host controller"). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-14-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: restructure PHY creationJohan Hovold
In preparation for supporting devicetree bindings which do not use a child node, move the PHY creation to probe() proper and parse the serdes resource in what is now the legacy devicetree helper. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-13-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: add register init helperJohan Hovold
Generalise the serdes initialisation helper so that it can be used to initialise all the PHY registers (e.g. serdes, tx, rx, pcs). Note that this defers the ungating of the PIPE clock somewhat, which is fine as it isn't needed until starting the PHY. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: use shorter tables identifiersJohan Hovold
The QMP drivers all use 'tbl' to refer to their register initialisation tables. For consistency use 'tbls' rather than 'tables' to refer to the new aggregate table structures. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221105145939.20318-9-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: clean up PHY lane initJohan Hovold
Clean up the PHY lane initialisation somewhat by adding further temporary variables and programming both tx and rx for the second lane after the first lane. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-8-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: rename PHY ops structureJohan Hovold
Rename the PHY operation structure so that it has a "phy_ops" suffix and move it next to the implementation. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: clean up probe initialisationJohan Hovold
Stop abusing the driver data pointer and instead pass the driver state structure directly to the initialisation helpers during probe. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: clean up device-tree parsingJohan Hovold
Since the QMP driver split there will be at most a single child node so drop the obsolete iteration construct. While at it, drop the verbose error logging that would have been printed also on probe deferrals. Note that there's no need to check if there are additional child nodes (the kernel is not a devicetree validator), but let's return an error if there are no child nodes at all for now. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: merge driver dataJohan Hovold
The PCIe QMP PHY driver only manages a single PHY so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: move device-id tableJohan Hovold
Move the device-id table below probe() and next to the driver structure to keep the driver callback functions grouped together. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-10phy: qcom-qmp-pcie: sort device-id tableJohan Hovold
Sort the device-id table by compatible string to make it easier to find and add new entries. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: add config sanity checksJohan Hovold
The driver expects every configuration to set the pwrdn_ctrl and phy_status masks. Add some probe WARN_ON_ONCE() to probe to catch any new driver support that fails to provide them. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-17-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: drop start-ctrl abstractionJohan Hovold
All PCIe PHYs need to start and stop the SerDes and PCS so drop the start-ctrl abstraction which is no longer needed since the QMP driver split. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-16-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: increase status polling periodJohan Hovold
It typically takes between one and two milliseconds for the PHY to become ready after starting it. Increase the tight 3--10 us polling period to the more reasonable 51--200 us. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221012085002.24099-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: clean up status pollingJohan Hovold
Clean up the status polling by dropping the ready bit mask which is no longer needed since the QMP driver split. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: fix ipq6018 initialisationJohan Hovold
The phy_status mask was never set for IPQ6018 which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: 520264db3bf9 ("phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: fix ipq8074-gen3 initialisationJohan Hovold
The phy_status mask was never set for IPQ8074 (gen3) which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: 334fad185415 ("phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: fix sc8180x initialisationJohan Hovold
The phy_status mask was never set for SC8180X which meant that the driver would not wait for the PHY to be initialised during power-on and would never detect PHY initialisation timeouts. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: replace power-down delayJohan Hovold
The power-down delay was included in the first version of the QMP driver as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). But as the vendor kernel do have a 1 ms delay *after* starting the PHY and before starting to poll the status it is possible that later contributors have simply not noticed that the mainline power-down delay is not equivalent. As the current delay before even starting the PHY is pretty much pointless and likely a mistake, move the delay after starting the PHY which avoids a few iterations of polling and speeds up startup by 1 ms (the poll loop otherwise takes about 1.8 ms). Note that MSM8998 has never used a power-down delay so add a flag to skip the delay in case starting the PHY is faster on MSM8998. This can be removed after someone takes a measurement. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012081241.18273-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: drop power-down delay configJohan Hovold
The power-down delay was included in the first version of the QMP driver as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). Let's keep the delay for now, but drop the redundant delay period configuration while increasing the unnecessarily low timer slack somewhat. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221012081241.18273-9-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-pcie: drop redundant ipq8074 power onJohan Hovold
The PCS initialisation table for IPQ8074 includes updates of the reset and start-control registers which is already handled explicitly by the driver during power on. Drop the redundant register write from the IPQ8074 configuration table and along with it the now unused "in-layout" configuration macro and code. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221012081241.18273-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp: drop superfluous commentsJohan Hovold
Drop some unnecessary or incorrect comments. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221012081241.18273-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp: drop regulator error messageJohan Hovold
Regulator core already logs an error message in case requesting a regulator fails so drop the mostly redundant error message from probe. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221012081241.18273-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-17phy: qcom-qmp-pcie: drop bogus register updateJohan Hovold
Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the PHY is powered on before configuring the registers and only the MSM8996 PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS initialisation table, may possibly require a second update afterwards. To make things worse, the POWER_DOWN_CONTROL register lies at a different offset on more recent SoCs so that the second update, which still used a hard-coded offset, would write to an unrelated register (e.g. a revision-id register on SC8280XP). As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop the bogus register update. Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #RB3 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221017065013.19647-12-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-17phy: qcom-qmp-pcie: clean up clock listsJohan Hovold
Keep the clock lists together and sorted by symbol name. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221017065013.19647-11-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-17phy: qcom-qmp-pcie: move power-down updateJohan Hovold
Move the power-down-control register update that powers on the PHY to the power-on handler so that it matches the power-off handler. Note that the power-on handler is currently always called directly after init. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221017065013.19647-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-17phy: qcom-qmp-pcie: clean up power-down handlingJohan Hovold
Always define the POWER_DOWN_CONTROL register instead of falling back to the v2 offset during power on and power off. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221017065013.19647-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit (git 2.34.1) at 2025-05-30 23:27:47 +0000