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path: root/drivers/phy/qualcomm
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2021-10-26phy: qcom-snps: Correct the FSEL_MASKSandeep Maheswaram
The FSEL_MASK which selects the refclock is defined incorrectly. It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7) in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog blocks ON during suspend. Fix this issue by correctly defining the FSEL_MASK. Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> Link: https://lore.kernel.org/r/1635135575-5668-1-git-send-email-quic_c_sanm@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-26phy: qcom-qmp: another fix for the sc8180x PCIe definitionDmitry Baryshkov
Commit f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") added SC8180X PCIe tables, but used sm8250_qmp_pcie_serdes_tbl as a serdes table because of the copy paste error. Commit bfccd9a71a08 ("phy: qcom-qmp: Fix sc8180x PCIe definition") corrected part of this mistake by pointing serdes_tbl to sc8180x_qmp_pcie_serdes_tbl, however the serdes_tbl_num field was not updated to use sc8180x table. So let's now fix the serdes_tbl_num field too. Fixes: bfccd9a71a08 ("phy: qcom-qmp: Fix sc8180x PCIe definition") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020155604.1374530-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-26phy: qcom-qusb2: Fix a memory leak on probeVladimir Zapolskiy
On success nvmem_cell_read() returns a pointer to a dynamically allocated buffer, and therefore it shall be freed after usage. The issue is reported by kmemleak: # cat /sys/kernel/debug/kmemleak unreferenced object 0xffff3b3803e4b280 (size 128): comm "kworker/u16:1", pid 107, jiffies 4294892861 (age 94.120s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<000000007739afdc>] __kmalloc+0x27c/0x41c [<0000000071c0fbf8>] nvmem_cell_read+0x40/0xe0 [<00000000e803ef1f>] qusb2_phy_init+0x258/0x5bc [<00000000fc81fcfa>] phy_init+0x70/0x110 [<00000000e3d48a57>] dwc3_core_soft_reset+0x4c/0x234 [<0000000027d1dbd4>] dwc3_core_init+0x68/0x990 [<000000001965faf9>] dwc3_probe+0x4f4/0x730 [<000000002f7617ca>] platform_probe+0x74/0xf0 [<00000000a2576cac>] really_probe+0xc4/0x470 [<00000000bc77f2c5>] __driver_probe_device+0x11c/0x190 [<00000000130db71f>] driver_probe_device+0x48/0x110 [<0000000019f36c2b>] __device_attach_driver+0xa4/0x140 [<00000000e5812ff7>] bus_for_each_drv+0x84/0xe0 [<00000000f4bac574>] __device_attach+0xe4/0x1c0 [<00000000d3beb631>] device_initial_probe+0x20/0x30 [<000000008019b9db>] bus_probe_device+0xa4/0xb0 Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210922233548.2150244-1-vladimir.zapolskiy@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-26phy: qcom-qmp: Add QCM2290 USB3 PHY supportShawn Guo
Enable QCM2290 USB3 PHY support by adding the qmp_phy_cfg data which are taken from downstream kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210927064829.5752-3-shawn.guo@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-05phy: qcom-qusb2: Add missing vdd supplyShawn Guo
Per downstream kernel, beside vdda-pll and vdda-phy-dpdm, vdd is also a required supply for QUSB2 PHY digital circuit operation. The driver works right now likely because firmware already sets it up. Add it for correctness and completeness. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210928022002.26286-3-shawn.guo@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01phy: qcom-qmp: Make use of the helper function devm_add_action_or_reset()Cai Huoqing
The helper function devm_add_action_or_reset() will internally call devm_add_action(), and gif devm_add_action() fails then it will execute the action mentioned and return the error code. So use devm_add_action_or_reset() instead of devm_add_action() to simplify the error handling, reduce the code. Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210922130017.692-1-caihuoqing@baidu.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01phy: qcom-qusb2: Add compatible for QCM2290Shawn Guo
Add compatible for QCM2290 QUSB2 device which reuses SM6115 configuration. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919031110.25064-3-shawn.guo@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-23phy: qcom-qmp: Add support for SM6115 UFS phyIskren Chernev
Add the tables and constants for init sequences for UFS QMP phy found in SM4250/6115 SoC. The phy is a variation of the v2 phy, but is mistakenly labeled as v3-660 in downstream sources. QSERDES COM, RX, TX registers match fully existing v2 registers, with a few additions. PCS registers don't have much in common, but there are no clashes with existing ones so new registers were added to existing v2 PCS pack. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210821155657.893165-3-iskren.chernev@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-20phy: qmp: Provide unique clock names for DP clocksBjorn Andersson
The USB/DP combo PHY exposes the "qmp_dp_phy_pll_link_clk" and "qmp_dp_phy_pll_vco_div_clk" clocks, that are consumed by the display clock controller. But for boards with multiple enabled QMP USB/DP combo instances the hard coded names collides - and hence only the first probed device is allowed to register. Given that clocks are no longer reference globally by name and it's possible to replace the hard coded names by something unique, but still user friendly. The two new clock names are based on dev_name() and results in names such as "88ee000.phy::link_clk" and "88ee000.phy::vco_div_clk". Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210722030738.3385821-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-06phy: qcom-qmp: add USB3 PHY support for IPQ6018Baruch Siach
Initialization is identical to the IPQ8074 USB3 PHY. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/6eec7ef4ecd1e8360ebe8e425151121684e997ed.1628085910.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-06phy: qcom: qmp: Add SC8180x USB/DP comboBjorn Andersson
The two USB QMPs are USB/DP compbo PHYs, add the compatible for this combination to allow DP output. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210721225630.3035861-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-06phy: qualcomm: phy-qcom-usb-hs: repair non-kernel-doc commentRandy Dunlap
Fix errant use of "/**" to begin a comment although the comment is not kernel-doc notation. Just use "/*" instead. Fixes this kernel-doc warning: drivers/phy/qualcomm/phy-qcom-usb-hs.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Copyright (C) 2016 Linaro Ltd Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20210723022548.25695-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-07-22phy: qcom-qmp: Fix sc8180x PCIe definitionBjorn Andersson
A copy paste error was snuck into the patch going upstream that made the SC8180x PCIe PHY use the SM8250 serdes table, but while this works there's some differences in the tables (and the SC8180x was left dangling). So correct the SC8180x definition to use the SC8180x serdes table. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210721163029.2813497-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-07-20phy: qcom-qmp: Add sc8180x PCIe supportBjorn Andersson
The Qualcomm SC8180x platform has 4 PCIe controllers and PHYs, typically used to connect things such as a modem or NVME storage device. Add the programming sequence to get the PHYs up and running. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210629004509.1788286-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-07-05Merge tag 'usb-5.14-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt updates from Greg KH: "Here is the big set of USB and Thunderbolt patches for 5.14-rc1. Nothing major here just lots of little changes for new hardware and features. Highlights are: - more USB 4 support added to the thunderbolt core - build warning fixes all over the place - usb-serial driver updates and new device support - mtu3 driver updates - gadget driver updates - dwc3 driver updates - dwc2 driver updates - isp1760 host driver updates - musb driver updates - lots of other tiny things. Full details are in the shortlog. All of these have been in linux-next for a while now with no reported issues" * tag 'usb-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (223 commits) phy: qcom-qusb2: Add configuration for SM4250 and SM6115 dt-bindings: phy: qcom,qusb2: document sm4250/6115 compatible dt-bindings: usb: qcom,dwc3: Add bindings for sm6115/4250 USB: cdc-acm: blacklist Heimann USB Appset device usb: xhci-mtk: allow multiple Start-Split in a microframe usb: ftdi-elan: remove redundant continue statement in a while-loop usb: class: cdc-wdm: return the correct errno code xhci: remove redundant continue statement usb: dwc3: Fix debugfs creation flow usb: gadget: hid: fix error return code in hid_bind() usb: gadget: eem: fix echo command packet response issue usb: gadget: f_hid: fix endianness issue with descriptors Revert "USB: misc: Add onboard_usb_hub driver" Revert "of/platform: Add stubs for of_platform_device_create/destroy()" Revert "usb: host: xhci-plat: Create platform device for onboard hubs in probe()" Revert "arm64: dts: qcom: sc7180-trogdor: Add nodes for onboard USB hub" xhci: solve a double free problem while doing s4 xhci: handle failed buffer copy to URB sg list and fix a W=1 copiler warning xhci: Add adaptive interrupt rate for isoch TRBs with XHCI_AVOID_BEI quirk xhci: Remove unused defines for ERST_SIZE and ERST_ENTRIES ...
2021-06-24phy: qcom-qusb2: Add configuration for SM4250 and SM6115Iskren Chernev
The SM4250 and SM6115 uses the same register layout as MSM8996, but the tune sequence is a bit different. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210622203240.559979-4-iskren.chernev@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-31phy: qcom-qmp: remove redundant error of clock bulkChunfeng Yun
There is error log in clk_bulk_prepare/enable() Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1621229841-22984-1-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-31phy: qcom-qmp: Add support for SDX55 QMP PCIe PHYManivannan Sadhasivam
The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-31phy: qcom-qmp: Use phy_status field for the status bit offsetManivannan Sadhasivam
In preparation of the support for v4.20 PCIe PHY in SDX55, use a separate "phy_status" field for the status bit offset. This is needed because, the v4.20 PHY uses a different offset for the PHY Status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210427065400.18958-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-14phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xxSelvam Sathappan Periakaruppan
Based on code from downstream Codeaurora tree. The ipq60xx has one gen3 PCIe port. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/e24f2bedb8a7346018b58136bcb0a4004d8677a0.1620203062.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: add support for sm8250-usb3-dp phyDmitry Baryshkov
Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: rename common registersDmitry Baryshkov
A plenty of DP PHY registers are common between V3 and V4. To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: qcom-qmp: move DP functions to callbacksDmitry Baryshkov
In preparation to adding support for V4 DP PHY move DP functions to callbacks at struct qmp_phy_cfg. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: qcom-qmp: add hbr3_hbr2 voltage and premphasis swing tableKuogee Hsieh
Add hbr3_hbr2 voltage and premphasis swing table to support HBR3 link rate. Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-25phy: qualcomm: remove duplicate argumentZhang Yunkai
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by: Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: qcom-usb-hs: Fix fall-through warnings for ClangGustavo A. R. Silva
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20210305100219.GA142595@embeddedor Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: make a const array static, makes object smallerColin Ian King
Don't populate the const array cfg1_settings on the stack but instead make it static. Makes the object code smaller by 24 bytes: Before: text data bss dec hex filename 73585 20240 64 93889 16ec1 drivers/phy/qualcomm/phy-qcom-qmp.o After: text data bss dec hex filename 73465 20336 64 93865 16ea9 drivers/phy/qualcomm/phy-qcom-qmp.o (gcc version 10.2.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add support for SM8350 UFS phyVinod Koul
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add UFS V5 registers found in SM8350Vinod Koul
Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qualcomm: usb28nm: Add MDM9607 init sequenceKonrad Dybcio
This is required to bring up the PHY on MDM9607-based boards. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qusb2: add QUSB2 support for IPQ6018Kathiravan T
Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X USB phyBjorn Andersson
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are either the same or very similar to the same found in SM8150. Add a compatible for this, reusing the existing SM8150 USB phy config. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X UFS phyBjorn Andersson
The UFS phy found in the Qualcomm SC8180X is either the same or very similar to the phy present in SM8150, so add a compatible and reuse the SM8150 configuration. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Add configuration for SDM660AngeloGioacchino Del Regno
The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Allow specifying default clock schemeAngeloGioacchino Del Regno
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qmp: Add SM8350 USB QMP PHYsJack Pham
Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-17phy: qcom-qmp: Add support for SDX55 QMP PHYManivannan Sadhasivam
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-12-09Merge tag 'phy-for-5.11' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.11 - New phy drivers: - Mediatek MT7621 PCIe PHY (promoted from staging) - Ingenic USB phy driver supporting JZ4775 and X2000 - Intel Keem Bay USB PHY driver - Marvell USB HSIC PHY driver supporting MMP3 SoC - AXG MIPI D-PHY driver - Updates: - Conversion to YAML binding for: - Broadcom SATA PHY - Cadence Sierra PHY bindings - STM32 USBC Phy - Support for Exynos5433 PCIe PHY - Support for Qualcomm SM8250 PCIe QMP PHY - Support for Exynos5420 USB2 phy - devm_platform_ioremap_resource conversion for bunch of drivers * tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) drm/mediatek: avoid dereferencing a null hdmi_phy on an error message phy: ingenic: depend on HAS_IOMEM phy: mediatek: statify mtk_hdmi_phy_driver dt-bindings: phy: Convert Broadcom SATA PHY to YAML devicetree: phy: rockchip-emmc add output-tapdelay-select phy: rockchip-emmc: output tap delay dt property PHY: Ingenic: Add USB PHY driver using generic PHY framework. dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000. USB: PHY: JZ4770: Remove unnecessary function calls. devicetree: phy: rockchip-emmc: pulldown property phy: rockchip: set pulldown for strobe line in dts phy: renesas: rcar-gen3-usb2: disable runtime pm in case of failure phy: mediatek: allow compile-testing the hdmi phy phy/rockchip: Make PHY_ROCKCHIP_INNO_HDMI depend on HAS_IOMEM to fix build error phy: samsung: Merge Kconfig for Exynos5420 and Exynos5250 phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig phy: mediatek: Make PHY_MTK_{XSPHY, TPHY} depend on HAS_IOMEM and OF_ADDRESS to fix build errors phy: tegra: xusb: Fix usb_phy device driver field phy: amlogic: replace devm_reset_control_array_get() ...
2020-11-16phy: qualcomm: Fix 28 nm Hi-Speed USB PHY OF dependencyBryan O'Donoghue
This Kconfig entry should declare a dependency on OF Fixes: 67b27dbeac4d ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-3-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: usb: Fix SuperSpeed PHY OF dependencyBryan O'Donoghue
This Kconfig entry should declare a dependency on OF Fixes: 6076967a500c ("phy: qualcomm: usb: Add SuperSpeed PHY driver") Reported-by: kernel test robot <lkp@intel.com> Link: https://lkml.org/lkml/2020/11/13/414 Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-2-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-10-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qcom-qmp: Add SM8250 PCIe QMP PHYsManivannan Sadhasivam
SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-28phy: qcom-qmp: Initialize another pointer to NULLStephen Boyd
This probe function is too complicated and should be refactored. For now let's just set this variable to NULL and keep the static analysis tools happy. Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201026205942.2861828-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-02Merge tag 'phy-for-5.10' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next Vinod writes: phy for 5.9 - Core: - New PHY attribute for max_link_rate - New phy drivers: - Rockchip dphy driver moved from staging - Socionext UniPhier AHCI PHY driver - Intel LGM SoC USB phy - Intel Keem Bay eMMC PHY driver - Updates: - Support for imx8mp usb phy - Support for DP Phy and USB3+DP combo phy in QMP driver - Support for Qualcomm sc7180 DP phy - Support for cadence torrent PCIe and USB single linke and multilink configurations along with USB, SGMII/QSGMII configurations * tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: qcom-qmp: initialize the pointer to NULL phy: qcom-qmp: Add support for sc7180 DP phy phy: qcom-qmp: Add support for DP in USB3+DP combo phy phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify phy: qcom-qmp: Get dp_com I/O resource by index phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' phy: qcom-qmp: Move phy mode into struct qmp_phy dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy dt-bindings: phy: cdns,torrent-phy: add reset-names phy: rockchip-dphy-rx0: Include linux/delay.h phy: fix USB_LGM_PHY warning & build errors phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration phy: cadence-torrent: Add PCIe + USB multilink configuration phy: cadence-torrent: Add single link USB register sequences phy: cadence-torrent: Add single link SGMII/QSGMII register sequences phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals phy: cadence-torrent: Add PHY link configuration sequences for single link phy: cadence-torrent: Add clk changes for multilink configuration ...
2020-10-01phy: qcom-qmp: initialize the pointer to NULLVinod Koul
Smatch complains: drivers/phy/qualcomm/phy-qcom-qmp.c:3899 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_cfg'. drivers/phy/qualcomm/phy-qcom-qmp.c:3900 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_serdes'. drivers/phy/qualcomm/phy-qcom-qmp.c:3902 qcom_qmp_phy_probe() error: uninitialized symbol 'usb_cfg'. This is a warning but not a practical one as dp_cfg, dp_serdes and usb_cfg will be set and used when valid. So we can set the pointers to NULL to quiesce the warnings. Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201001070911.140019-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Add support for sc7180 DP phyStephen Boyd
Add the necessary compatible strings and phy data for the sc7180 USB3+DP combo phy. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-9-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Add support for DP in USB3+DP combo phyStephen Boyd
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplifyStephen Boyd
We can use the wrapper API here to save some lines and remove the need for the 'base' and 'res' local variable. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-7-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Get dp_com I/O resource by indexStephen Boyd
The dp_com resource is always at index 1 according to the dts files in the kernel. Get this resource by index so that we don't need to make future additions to the DT binding use 'reg-names'. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-6-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'Stephen Boyd
The serdes I/O region is where the PLL for the phy is controlled. Sometimes the PLL is shared between multiple phys, for example in the PCIe case where there are three phys inside the same wrapper. Other times the PLL is for a single phy, i.e. some USB3 phys. To complete the trifecta we have the USB3+DP combo phy where the USB3 and DP phys each have their own serdes region because they have their own PLL while they both share a common I/O region pertaining to the USB type-c pinout and cable orientation. Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can correlate PLL control to the phy that uses it. This allows us to support the USB3+DP combo phy in this driver. This isn't a problem for the 3-lane/phy PCIe phy because there is a common init function that is the only place the serdes region is programmed. Furthermore, move the configuration data that contains most of the register programming sequences to the qmp phy struct. This data isn't qmp wrapper specific. It is phy specific data used to tune various settings for things like pre-emphasis, bias, etc. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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