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path: root/drivers/pinctrl/renesas/pinctrl.c
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2023-03-30pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levelsGeert Uytterhoeven
Currently, the Renesas pin control driver supports pins that can switch their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. However, some SoCs have pins that can switch between 1.8V and 2.5V. Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE capability and voltage level flags by a 2-bit field, to cover three possible I/O voltage switching options. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert+renesas@glider.be
2023-03-16pinctrl: renesas: Drop support for Renesas-specific propertiesGeert Uytterhoeven
The last user of the Renesas-specific properties was converted to the standard properties in commit af897250ea54c6f2 ("ARM: dts: gose: use generic pinctrl properties in SDHI nodes") in v4.10. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/ff9c14781110bbf19b56b45dd1f01e6da90319ad.1678704441.git.geert+renesas@glider.be
2022-10-24pinctrl: renesas: Add missing header(s)Andy Shevchenko
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: Remove unneeded #include <linux/init.h>Geert Uytterhoeven
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fb71c409ea3ad76163496e305dc955ca8e84416d.1649681741.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Pass sh_pfc_soc_info to rcar_pin_to_bias_reg()Geert Uytterhoeven
Currently rcar_pin_to_bias_reg() takes a struct sh_pfc pointer, which is only available after the pin control driver has been initialized, thus preventing the checker from calling this function for validating consistency of the pin control tables. Fix this by replacing the parameter by a struct sh_pfc_soc_info pointer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3065a12dde606bacec9e5f14f10cabeaae75e265.1640270559.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Factor out .pin_to_portcr() address handlingGeert Uytterhoeven
All implementations of the .pin_to_portcr() method implement the same conversion from Port Control Register offset to virtual address. Factor it out into the two callers. Remove the pfc parameter, as it is no longer used. Note that the failure handling in r8a7740_pin_to_portcr() is pro forma, as the function is never called with an invalid pin number. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a485d4986a17259256988eb14e3a4c2b8d61c303.1640270559.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Remove unused pfc parameter from .pin_to_pocctrl()Geert Uytterhoeven
The pfc parameter of the .pin_to_pocctrl() method was never used. It is a relic of the old I/O voltage handling before commit 8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting"). Remove the parameter, as it prevents the checker from calling this function for validating consistency of the pin control tables. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/822133086f32618c7fc920123c6a96f5d4ea7ad6.1640270559.git.geert+renesas@glider.be
2022-01-24pinctrl: renesas: rcar: Do not enforce GPIO if already muxedWolfram Sang
For Renesas PFCs not setting .strict, we can snoop GPIOs which are already muxed to some other function. To actually make use of that, we shouldn't mux them back to GPIO if they have been already muxed to something. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211210113226.40111-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19pinctrl: renesas: Remove unneeded locking around sh_pfc_read() callsGeert Uytterhoeven
There is no need to acquire the spinlock when reading from a pin controller register: 1. Reading a single MMIO register is an atomic operation, 2. While sh_pfc_phys_to_virt() inside sh_pfc_read() has to traverse all mapped windows to find the appropriate virtual address, this does not need any locking, as the window mappings are never changed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2008ca99f0079fd5d4e640b7ef78710c98cc9f77.1637143108.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: r8a77995: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: rcar: Avoid changing PUDn when disabling biasGeert Uytterhoeven
When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be
2021-03-24pinctrl: renesas: Add support for R-Car SoCs with pull-down only pinsGeert Uytterhoeven
Currently, the common R-Car bias handling supports pin controllers with either: 1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers, for controlling both pin pull-up and pin pull-down, 2. A single pin Pull-Up control register (PUPR), for controlling pin pull-up. Add support for a variant of #2, where some bits in the single pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W, M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C. To describe such a register, SoC-specific drivers need to provide two instances of pinmux_bias_reg: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Factor out common R-Mobile bias handlingGeert Uytterhoeven
The pin control sub-drivers for SH/R-Mobile SoCs contain almost identical bias handling. The only SoC-specific part is the mapping from pin numbers to PORTnCR registers. Reduce code duplication by factoring out the bias handling to the common pinctrl.c code. Use a callback to handle the pin/register mapping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-4-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() staticGeert Uytterhoeven
Now all R-Car pin control drivers have been converted to the common R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a single place. Move it from core.c to pinctrl.c, make it static, and rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
2021-01-14pinctrl: renesas: Add I/O voltage level flagUlrich Hecht
This patch adds config macros describing the voltage levels available on a pin. The current default (3.3V/1.8V) maps to zero to avoid having to change existing PFC implementations. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIOGeert Uytterhoeven
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
2020-11-13pinctrl: renesas: r8a7778: Use common R-Car bias handlingGeert Uytterhoeven
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Factor out common R-Car Gen3 bias handlingGeert Uytterhoeven
All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-6-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Optimize sh_pfc_pin_configGeert Uytterhoeven
Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Singular/plural grammar fixesGeert Uytterhoeven
Fix a few singular vs. plural grammar issues in comments. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-3-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction()Geert Uytterhoeven
Commit b13431ed6eab808a ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-2-geert+renesas@glider.be
2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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