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path: root/drivers/pinctrl/renesas
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2021-01-14pinctrl: renesas: Implement unlock register masksUlrich Hecht
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12pinctrl: renesas: checker: Restrict checks to Renesas platformsGeert Uytterhoeven
When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin control driver runs sanity checks against the pin control tables. This may cause lots of output on the console, and can be annoying in ARM multi-platform kernels. Fix this by only running the checks when running on SuperH, or on a DT platform supported by the Renesas pin controller driver. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
2021-01-05pinctrl: remove empty lines in pinctrl subsystemZhaoyu Liu
Remove all empty lines at the end of functions in pinctrl subsystem, and make the code neat. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Zhaoyu Liu <zackaryliu@yeah.net> Link: https://lore.kernel.org/r/X98NP6NFK1Afzrgd@manjaro Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-11-23pinctrl: renesas: Fix fall-through warnings for ClangGustavo A. R. Silva
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/da20103af0c22424c5d08a12f7107771bf4c01c5.1605896059.git.gustavoars@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23pinctrl: renesas: r8a77965: Add QSPI[01] pins, groups and functionsLad Prabhakar
Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functionsLad Prabhakar
Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functionsLad Prabhakar
Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functionsLad Prabhakar
Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: Constify sh73a0_vccq_mc0_opsRikard Falkeborn
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the ops field in the regulator_desc struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIOGeert Uytterhoeven
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles GPIOs, too. To reduce code size when compiling a kernel supporting only modern SoCs, most, but not all, of the GPIO functionality is protected by checks for CONFIG_PINCTRL_SH_FUNC_GPIO. Factor out the remaining parts when not needed: 1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input resp. output capabilities (SuperH and SH/R-Mobile). 2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO pins to interrupt numbers (SH/R-Mobile). 3. sh_pfc_gpio_set_direction() configures GPIO direction, called from the GPIO driver through pinctrl_gpio_direction_{in,out}put() (SH/R-Mobile). Unfortunately this function cannot just be moved to drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of sh_pfc_pinctrl, which is internal to drivers/pinctrl/renesas/pinctrl.c. While code size reduction is minimal, this does help in documenting depencies. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
2020-11-13pinctrl: renesas: r8a7778: Use common R-Car bias handlingGeert Uytterhoeven
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD) registers, like R-Car Gen3 and RZ/G2. Update the function to handle SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car Gen1/Gen2 and RZ/G1. Reduce code duplication by converting the R-Car M1A pin control driver to use the common handler. Note that this changes behavior in case the (invalid!) option "bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored silently; after this change, it is considered the same as "bias-pull-up". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
2020-11-13pinctrl: renesas: r8a7778: Use physical addresses for PUPR regsGeert Uytterhoeven
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car M1A uses register offsets instead of register physical addresses. This is different from the handling on other R-Car parts. Convert the bias handling from register offsets to physical addresses. This increases uniformity, and prepares for consolidation of the bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Factor out common R-Car Gen3 bias handlingGeert Uytterhoeven
All pin control drivers for R-Car Gen3 SoCs contain identical bias handling. Reduce code duplication by moving it to the common pinctrl.c code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-6-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Optimize sh_pfc_pin_configGeert Uytterhoeven
Shrink sh_pfc_pin_config from 8 to 2 bytes: - The mux_set flag can be removed, as a non-zero mark value means the same (zero = PINMUX_RESERVED is an invalid mark value), - The gpio_enabled flag needs only a single bit, - Mark values are small integers, and can easily fit in a 15-bit bitfield. This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Reorder struct sh_pfc_pin to remove holeGeert Uytterhoeven
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Singular/plural grammar fixesGeert Uytterhoeven
Fix a few singular vs. plural grammar issues in comments. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-3-geert+renesas@glider.be
2020-11-13pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction()Geert Uytterhoeven
Commit b13431ed6eab808a ("pinctrl: sh-pfc: Remove incomplete flag "cfg->type"") removed the last statement in between the goto and the label. Hence remove both. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028151637.1734130-2-geert+renesas@glider.be
2020-11-13pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[34]Biju Das
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs. Optimize pinctrl image size for RZ/G1[MN], when support for R-Car M2-W/M2-N (R8A779[13]) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742Biju Das
This driver supports both RZ/G1H and R-Car H2 SoCs. Optimize pinctrl image size for RZ/G1H, when support for R-Car H2 (R8A7790) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0Biju Das
This driver supports both RZ/G2E and R-Car E3 SoCs. Optimize pinctrl image size for RZ/G2E, when support for R-Car E3 (R8A77990) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1Biju Das
This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1Biju Das
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1Biju Das
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2 (R8A77951) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-10-26pinctrl: renesas: r8a7790: Add VIN1-B and VIN2-G pins, groups and functionsLad Prabhakar
Add pins, groups and functions for the VIN1-B [data/sync/field/clkenb/clk] and VIN2-G8. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200917195924.20384-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-15pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc codeGeert Uytterhoeven
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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