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path: root/drivers/pinctrl/renesas
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2021-10-15pinctrl: renesas: checker: Prefix common checker outputGeert Uytterhoeven
Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for easier grepping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Fix bias checks on SoCs with pull-down only pinsGeert Uytterhoeven
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Move overlapping field checkGeert Uytterhoeven
Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: checker: Fix off-by-one bug in drive register checkGeert Uytterhoeven
The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e07ad0a1ec ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: Fix save/restore on SoCs with pull-down only pinsGeert Uytterhoeven
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be
2021-10-15pinctrl: renesas: r8a779[56]x: Add MediaLB pinsAndrey Gusakov
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com [geert: Fix automotive handling] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24pinctrl: renesas: rzg2l: Fix missing port register 21hBiju Das
Remove the duplicate port register 22h and replace it with missing port register 21h. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922074140.22178-1-biju.das.jz@bp.renesas.com Fixes: c4c4637eb57f2a25 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-13pinctrl: renesas: No need to initialise global staticsJason Wang
Global static variables don't need to be initialized to 0, because the compiler will initialize them. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Link: https://lore.kernel.org/r/20210906134040.96642-1-wangborong@cdjrlc.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-08-13pinctrl: renesas: Add RZ/G2L pin and gpio controller driverLad Prabhakar
Add support for pin and gpio controller driver for RZ/G2L SoC. Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-07-27pinctrl: renesas: Fix pin control matching on R-Car H3e-2GGeert Uytterhoeven
As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: r8a77995: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: rcar: Avoid changing PUDn when disabling biasGeert Uytterhoeven
When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a77980: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up and pull-down handling for the R-Car V3H SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/448f47ccd89d9bc8621c7fda8c81508deb05cb82.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a77970: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR) and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7794: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car E2 and RZ/G1E SoCs, using the common R-Car bias handling. Note that on RZ/G1E, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/f78da2ba937ce98ae9196f4ee54149a5214fd545.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7792: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (EDBGREQ) handling for the R-Car V2H SoC, using the common R-Car bias handling. Note that the R-Car V2H Hardware User's Manual Rev. 1.00 says that the LSI Pin Pull-Up Control Register 11 (PUPR11) controls pull-ups for the {SCK,WS,SDATA}[01] pins. These are assumed to be typos, as R-Car V2H has only Serial Sound Interface channels 3 and 4. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/48d2abdd63ee43ed99cb32ed4a5f4d76ba563162.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7790: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias handling. Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a77470: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for the RZ/G1C SoC, using the common R-Car bias handling. Note that on RZ/G1C, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/18c8ebf9fa9e239253a723857e9dffeec775db7e.1619785375.git.geert+renesas@glider.be
2021-05-11pinctrl: renesas: r8a779{51,6,65}: Reduce non-functional differencesGeert Uytterhoeven
Change whitespace in the pin control drivers for R-Car H3 ES2.0+, R-Car M3-W/M3-W+, and R-Car M3-N, to reduce the differences among these very similar drivers. These changes have no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/527b45ebfc664a80e41cb0136677db7260e11437.1619785375.git.geert+renesas@glider.be
2021-05-11pinctrl: renesas: r8a7778: Remove unused PORT_GP_PUP_1() macroGeert Uytterhoeven
The last user was removed in commit dd1f760bffcee2c5 ("pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macro"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/129147ac57f5e931cc7108db0a6483b803a1b8f4.1619785375.git.geert+renesas@glider.be
2021-05-11pinctrl: renesas: r8a77990: Drop bogus PUEN_ prefixes in commentsGeert Uytterhoeven
The "PUEN_" prefixes are part of the bit names of the PUEN registers, while the comments should refer to the actual pin names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/9ea85ae8973f6d9b3d10f02f0d9b4ab6a086ec63.1619785375.git.geert+renesas@glider.be
2021-05-11pinctrl: renesas: r8a77990: JTAG pins do not have pull-down capabilitiesGeert Uytterhoeven
Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flags from their pin descriptions. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/da4b2d69955840a506412f1e8099607a0da97ecc.1619785375.git.geert+renesas@glider.be
2021-05-11pinctrl: renesas: r8a7796: Add missing bias for PRESET# pinGeert Uytterhoeven
R-Car Gen3 Hardware Manual Errata for Rev. 0.52 of Nov 30, 2016, added the configuration bit for bias pull-down control for the PRESET# pin on R-Car M3-W. Add driver support for controlling pull-down on this pin. Fixes: 2d40bd24274d2577 ("pinctrl: sh-pfc: r8a7796: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c479de5b3f235c2f7d5faea9e7e08e6fccb135df.1619785375.git.geert+renesas@glider.be
2021-03-24pinctrl: renesas: r8a7791: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, using the common R-Car bias handling. Note that on RZ/G1 SoCs, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-7-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Add support for R-Car SoCs with pull-down only pinsGeert Uytterhoeven
Currently, the common R-Car bias handling supports pin controllers with either: 1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers, for controlling both pin pull-up and pin pull-down, 2. A single pin Pull-Up control register (PUPR), for controlling pin pull-up. Add support for a variant of #2, where some bits in the single pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W, M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C. To describe such a register, SoC-specific drivers need to provide two instances of pinmux_bias_reg: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Add PORT_GP_CFG_7 macrosGeert Uytterhoeven
Add PORT_GP_CFG_7() and PORT_GP_7() helper macros, to be used by the r8a7791 subdriver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-5-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Factor out common R-Mobile bias handlingGeert Uytterhoeven
The pin control sub-drivers for SH/R-Mobile SoCs contain almost identical bias handling. The only SoC-specific part is the mapping from pin numbers to PORTnCR registers. Reduce code duplication by factoring out the bias handling to the common pinctrl.c code. Use a callback to handle the pin/register mapping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-4-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Move R-Car bias helpers to sh_pfc.hGeert Uytterhoeven
The Renesas Pin Function Controller driver uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Hence move the R-Car bias helper declarations from core.h to sh_pfc.h, and drop the inclusion of core.h from SoC-specific drivers that no longer need it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() staticGeert Uytterhoeven
Now all R-Car pin control drivers have been converted to the common R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a single place. Move it from core.c to pinctrl.c, make it static, and rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
2021-03-10pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A77965 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-5-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A77990 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10pinctrl: renesas: r8a7796: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A7796 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10pinctrl: renesas: r8a77951: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A77951 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-18Merge tag 'renesas-pinctrl-for-v5.12-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.12 - Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC.
2021-01-14pinctrl: renesas: r8a779a0: Add TPU pins, groups and functionsUlrich Hecht
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add TMU pins, groups and functionsUlrich Hecht
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functionsUlrich Hecht
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC driver. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add PWM pins, groups and functionsUlrich Hecht
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functionsUlrich Hecht
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add MMC pins, groups and functionsUlrich Hecht
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and functionUlrich Hecht
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functionsUlrich Hecht
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add DU pins, groups and functionUlrich Hecht
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functionsUlrich Hecht
This patch adds CANFD 0-7 and CANFD clock pinmux support for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functionsUlrich Hecht
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and PTP pins for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add I2C pins, groups and functionsUlrich Hecht
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functionsUlrich Hecht
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Initial R8A779A0 (V3U) PFC supportUlrich Hecht
This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC, including bias, drive strength and voltage control. Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Add PORT_GP_CFG_{2,31} macrosUlrich Hecht
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Add I/O voltage level flagUlrich Hecht
This patch adds config macros describing the voltage levels available on a pin. The current default (3.3V/1.8V) maps to zero to avoid having to change existing PFC implementations. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2024-05-23 22:47:47 +0000