| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-11-16 | pinctrl: tegra: Return const pointer from tegra_pinctrl_get_group() | Prathamesh Shete | |
| Instead of returning const pointer from tegra_pinctrl_get_group() the return value is being casted. This change helps return const pointer. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2021-10-26 | pinctrl: tegra: Fix warnings and error | Prathamesh Shete | |
| Fix warnings are errors caused by commit a42c7d95d29e ("pinctrl: tegra: Use correct offset for pin group"). Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2021-10-26 | pinctrl: tegra: Use correct offset for pin group | Prathamesh Shete | |
| Function tegra_pinctrl_gpio_request_enable() and tegra_pinctrl_gpio_disable_free() uses pin offset instead of group offset, causing the driver to use wrong offset to enable gpio. Add a helper function tegra_pinctrl_get_group() to parse the pin group and determine correct offset. Signed-off-by: Kartik K <kkartik@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211025110959.27751-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2020-06-16 | pinctrl: tegra: Use noirq suspend/resume callbacks | Vidya Sagar | |
| Use noirq suspend/resume callbacks as other drivers which implement noirq suspend/resume callbacks (Ex:- PCIe) depend on pinctrl driver to configure the signals used by their respective devices in the noirq phase. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200604174935.26560-1-vidyas@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2020-03-27 | pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 | Thierry Reding | |
| Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2020-03-27 | pinctrl: tegra: Do not add default pin range on Tegra194 | Thierry Reding | |
| On Tegra194, almost all of the pin control programming happens in early boot firmware, so there is no use in having a pin range defined for all the pins. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2020-03-27 | pinctrl: tegra: Pass struct tegra_pmx for pin range check | Thierry Reding | |
| Pass the struct tegra_pmx when checking for the pin range in device tree. This makes the call site a bit easier to read and will help keep that readability in a subsequent patch. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-7-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2020-01-07 | pinctrl: tegra: fix missing __iomem in suspend/resume | Ben Dooks (Codethink) | |
| The functions should have __iomem on the register pointer so add that to silence the following sparse warnings: drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: got void [noderef] <asn:2> * drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: expected void const volatile [noderef] <asn:2> *addr drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: got unsigned int [usertype] * drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: expected unsigned int [usertype] *regs drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: got void [noderef] <asn:2> * drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces) drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: expected void volatile [noderef] <asn:2> *addr drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: got unsigned int [usertype] * Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-11-05 | pinctrl: use devm_platform_ioremap_resource() to simplify code | YueHaibing | |
| devm_platform_ioremap_resource() internally have platform_get_resource() and devm_ioremap_resource() in it. So instead of calling them separately use devm_platform_ioremap_resource() directly. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-08-21 | pinctrl: tegra: Flush pinctrl writes during resume | Sowjanya Komatineni | |
| This patch adds pinctrl register read to flush all the prior pinctrl writes and then adds barrier for pinctrl register read to complete during resume to make sure all pinctrl changes are effective. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-08-21 | pinctrl: tegra: Fix write barrier placement in pmx_writel | Sowjanya Komatineni | |
| pmx_writel uses writel which inserts write barrier before the register write. This patch has fix to replace writel with writel_relaxed followed by a readback and memory barrier to ensure write operation is completed for successful pinctrl change. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1565984527-5272-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-08-05 | pinctrl: tegra: Add suspend and resume support | Sowjanya Komatineni | |
| This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-07-13 | Merge tag 'pinctrl-v5.3-1' of ↵ | Linus Torvalds | |
| git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ... | |||
| 2019-06-25 | pinctrl: tegra: Add bitmask support for parked bits | Thierry Reding | |
| Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 | Thomas Gleixner | |
| Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |||
| 2019-06-01 | pinctrl: tegra: Support 32 bit register access | Krishna Yarlagadda | |
| Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2018-09-20 | pinctrl: tegra: do not export tegra_pinctrl_probe | Stefan Agner | |
| No user of tegra_pinctrl_probe can be built as a module, hence exporting the symbol is not necessary. Drop EXPORT_SYMBOL_GPL. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2018-07-29 | pinctrl: tegra: define GPIO compatible node per SoC | Stefan Agner | |
| Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2018-06-12 | treewide: devm_kzalloc() -> devm_kcalloc() | Kees Cook | |
| The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org> | |||
| 2018-05-16 | pinctrl: tegra20: Provide CDEV1/2 clock muxes | Dmitry Osipenko | |
| Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2018-01-03 | pinctrl: tegra: Delete two error messages for a failed memory allocation in ↵ | Markus Elfring | |
| tegra_pinctrl_probe() Omit extra messages for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2017-05-29 | pinctrl: tegra: clean up modular vs. non-modular distinctions | Paul Gortmaker | |
| None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get similar changes, so they are handled in batch. We remove module.h from code that isn't doing anything modular at all; if they have __init sections, then replace it with init.h. A couple drivers have module_exit() code that is essentially orphaned, and so we remove that. Quite a few bool drivers (hence non-modular) are converted over to to builtin_platform_driver(). Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Pritesh Raithatha <praithatha@nvidia.com> Cc: Ashwini Ghuge <aghuge@nvidia.com> Cc: linux-gpio@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-05-30 | Revert "Revert "pinctrl: tegra: avoid parked_reg and parked_bank"" | Linus Walleij | |
| This reverts commit 0d5358330c20d50e52e3e65ff07a5db8007041fc. | |||
| 2016-05-13 | Revert "pinctrl: tegra: avoid parked_reg and parked_bank" | Linus Walleij | |
| This reverts commit 1d18a3f0f0809f6c71f1f6e9e268ee904ce0b588. | |||
| 2016-05-11 | pinctrl: tegra: avoid parked_reg and parked_bank | Laxman Dewangan | |
| NVIDIA's Tegra210 support the park bit to make pinmux configuration enable/disable. If parked bit is 1 then configuration does not apply and if it is 0 then pinmux configuration applies. This is to support to avoid any glitch in pinmux configurations. The parked bit is part of mux register and mux bank and hence it is not required to have member for the parked_reg and parked bank very similar to other bit field of the same register. Remove the need of the parked register and parked bank and get whether parked function supported or not by parked_bit. This is to make the parked bit handling same as other fields of mux registers. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-05-11 | pinctrl: tegra: Correctly check the supported configuration | Laxman Dewangan | |
| The pincontrol registers of Tegra chips has multiple filed per registers. There is two type of registers mux and drive. All configurations belongs to one of these registers. If any configurations are supported then <config>_bit is set to bit position of these registers otherwise -1 to not support it. The member is defined as s32 <config>_bit:6; So if config is not supported ifor given SoC then it is set to -1 in soc pinmmux table. In common driver code, to find out that given config is supported or not, it is checked as: s8 bit = <config>_bit; if (bit > 31) { /* Not supported config */ } But in this case, bit is s8 and hence for non supporting it is -1. Correct the check as: if (bit < 0) { /* Not supported config */ } Fixes: e4c02dced975cb ("pinctrl: tegra: use signed bitfields for optional fields") Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-04-21 | pinctrl: tegra: Use devm_pinctrl_register() for pinctrl registration | Laxman Dewangan | |
| Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-04-14 | pinctrl: tegra: clear park bit for all pins | Rhyland Klein | |
| Parking bits might not be cleared by the bootloader properly (if for instance it doesn't use the device configured by that pin). Clear the park bits for all the pins during pinctrl probe. This is present on T210 platforms but not earlier ones, so for earlier generations, set parked_reg = -1 to disable. The park bit is used to prevent glitching when reprogramming pinctrl registers. Based on work by: Shravani Dingari <shravanid@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-04-01 | pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map | Irina Tirdea | |
| Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
| 2016-02-05 | pinctrl: tegra: move Tegra pinctrl drivers to sub-directory | Masahiro Yamada | |
| Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |||
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index : linux-arm.git | |
| Russell King's ARM Linux kernel tree | Russell King |
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