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path: root/drivers/pinctrl/tegra/pinctrl-tegra194.c
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2021-11-16pinctrl: tegra194: remove duplicate initializer againArnd Bergmann
An earlier bugfix removed a duplicate field initializer in a macro, but it seems that this came back with the following update: drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: error: initialized field overwritten [-Werror=override-init] 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: note: (near initialization for 'tegra194_groups[0].drv_reg') 1341 | .drv_reg = ((r)), \ | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1392 | #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4' 1631 | drive_##pg_name, \ | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP' 1636 | PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), | ^~~~~~~~ Remove it again. Fixes: 613c0826081b ("pinctrl: tegra: Add pinmux support for Tegra194") Fixes: 92cadf68e50a ("pinctrl: tegra: pinctrl-tegra194: Do not initialise field twice") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211104133645.1186968-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-24pinctrl: tegra: Add pinmux support for Tegra194Prathamesh Shete
This change adds pinmux table entries for Tegra194 Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/r/20211018121815.3017-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-16pinctrl: tegra: pinctrl-tegra194: Do not initialise field twiceLee Jones
Both PIN_PINGROUP_ENTRY_Y() and DRV_PINGROUP_ENTRY_Y() macros are called for each of the 2 pin groups defined here, and both of them initialise 'drv_reg', causing the compiler to complain. Only initialise 'drv_reg' once. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: warning: initialized field overwritten [-Woverride-init] 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:105:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 105 | DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_clkreq_n_pgg0’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:128:2: note: in expansion of macro ‘PINGROUP’ 128 | PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: note: (near initialization for ‘tegra194_groups[0].drv_reg’) 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:105:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 105 | DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_clkreq_n_pgg0’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:128:2: note: in expansion of macro ‘PINGROUP’ 128 | PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: warning: initialized field overwritten [-Woverride-init] 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:107:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 107 | DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_rst_n_pgg1’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:130:2: note: in expansion of macro ‘PINGROUP’ 130 | PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, | ^~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:71:14: note: (near initialization for ‘tegra194_groups[1].drv_reg’) 71 | .drv_reg = ((r)), | ^ drivers/pinctrl/tegra/pinctrl-tegra194.c:107:2: note: in expansion of macro ‘DRV_PINGROUP_ENTRY_Y’ 107 | DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:124:3: note: in expansion of macro ‘drive_pex_l5_rst_n_pgg1’ 124 | drive_##pg_name, | ^~~~~~ drivers/pinctrl/tegra/pinctrl-tegra194.c:130:2: note: in expansion of macro ‘PINGROUP’ 130 | PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, | ^~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-23-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27pinctrl: tegra: Add SFIO/GPIO programming on Tegra194Thierry Reding
Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27pinctrl: tegra: Renumber the GG.0 and GG.1 pinsThierry Reding
There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27pinctrl: tegra: Do not add default pin range on Tegra194Thierry Reding
On Tegra194, almost all of the pin control programming happens in early boot firmware, so there is no use in having a pin range defined for all the pins. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27pinctrl: tegra: Fix whitespace issues for improved readabilityThierry Reding
Fix a few whitespace inconsistencies to make the code easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-5-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: tegra: Add bitmask support for parked bitsThierry Reding
Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: tegra: Add Tegra194 pinmux driverKrishna Yarlagadda
Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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