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path: root/drivers/platform/x86/intel_pmc_core.c
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2019-11-21platform/x86: intel_pmc_core: Add Comet Lake (CML) platform support to ↵Gayatri Kammela
intel_pmc_core driver Add Comet Lake to the list of the platforms that intel_pmc_core driver supports for pmc_core device. Just like Ice Lake, Comet Lake can also reuse all the Cannon Lake PCH IPs. No additional effort is needed to enable but to simply reuse them. Cc: Mario Limonciello <mario.limonciello@dell.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Kan Liang <kan.liang@intel.com> Cc: David E. Box <david.e.box@intel.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-11-21platform/x86: intel_pmc_core: Fix the SoC naming inconsistencyGayatri Kammela
Intel's SoCs follow a naming convention which spells out the SoC name as two words instead of one word (E.g: Cannon Lake vs Cannonlake). Thus fix the naming inconsistency across the intel_pmc_core driver, so future SoCs can follow the naming consistency as below. Cometlake -> Comet Lake Tigerlake -> Tiger Lake Elkhartlake -> Elkhart Lake Cc: Mario Limonciello <mario.limonciello@dell.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Kan Liang <kan.liang@intel.com> Cc: David E. Box <david.e.box@intel.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Cc: Tony Luck <tony.luck@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-09-16Merge tag 'platform-drivers-x86-v5.4-1' of ↵Linus Torvalds
git://git.infradead.org/linux-platform-drivers-x86 Pull x86 platform-drivers updates from Andy Shevchenko: - ASUS WMI driver got a couple of updates, i.e. support of FAN is fixed for recent products and the charge threshold support has been added - Two uknown key events for Dell laptops are being ignored now to avoid spamming users with harmless messages - HP ZBook 17 G5 and ASUS Zenbook UX430UNR got accelerometer support. - Intel CherryTrail platforms had a regression with wake up. Now it's fixed - Intel PMC driver got fixed in order to work nicely in Xen environment - Intel Speed Select driver provides bucket vs core count relationship. Besides that the tools has been updated for better output - The PrivacyGuard is enabled on Lenovo ThinkPad laptops - Three tablets - Trekstor Primebook C11B 2-in-1, Irbis TW90 and Chuwi Surbook Mini - got touchscreen support * tag 'platform-drivers-x86-v5.4-1' of git://git.infradead.org/linux-platform-drivers-x86: (53 commits) MAINTAINERS: Switch PDx86 subsystem status to Odd Fixes platform/x86: asus-wmi: Refactor charge threshold to use the battery hooking API platform/x86: asus-wmi: Rename CHARGE_THRESHOLD to RSOC platform/x86: asus-wmi: Reorder ASUS_WMI_CHARGE_THRESHOLD tools/power/x86/intel-speed-select: Display core count for bucket platform/x86: ISST: Allow additional TRL MSRs tools/power/x86/intel-speed-select: Fix memory leak tools/power/x86/intel-speed-select: Output success/failed for command output tools/power/x86/intel-speed-select: Output human readable CPU list tools/power/x86/intel-speed-select: Change turbo ratio output to maximum turbo frequency tools/power/x86/intel-speed-select: Switch output to MHz tools/power/x86/intel-speed-select: Simplify output for turbo-freq and base-freq tools/power/x86/intel-speed-select: Fix cpu-count output tools/power/x86/intel-speed-select: Fix help option typo tools/power/x86/intel-speed-select: Fix package typo tools/power/x86/intel-speed-select: Fix a read overflow in isst_set_tdp_level_msr() platform/x86: intel_int0002_vgpio: Use device_init_wakeup platform/x86: intel_int0002_vgpio: Fix wakeups not working on Cherry Trail platform/x86: compal-laptop: Initialize "value" in ec_read_u8() platform/x86: touchscreen_dmi: Add info for the Trekstor Primebook C11B 2-in-1 ...
2019-09-07platform/x86: intel_pmc_core: Do not ioremap RAMM. Vefa Bicakci
On a Xen-based PVH virtual machine with more than 4 GiB of RAM, intel_pmc_core fails initialization with the following warning message from the kernel, indicating that the driver is attempting to ioremap RAM: ioremap on RAM at 0x00000000fe000000 - 0x00000000fe001fff WARNING: CPU: 1 PID: 434 at arch/x86/mm/ioremap.c:186 __ioremap_caller.constprop.0+0x2aa/0x2c0 ... Call Trace: ? pmc_core_probe+0x87/0x2d0 [intel_pmc_core] pmc_core_probe+0x87/0x2d0 [intel_pmc_core] This issue appears to manifest itself because of the following fallback mechanism in the driver: if (lpit_read_residency_count_address(&slp_s0_addr)) pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; The validity of address PMC_BASE_ADDR_DEFAULT (i.e., 0xFE000000) is not verified by the driver, which is what this patch introduces. With this patch, if address PMC_BASE_ADDR_DEFAULT is in RAM, then the driver will not attempt to ioremap the aforementioned address. Signed-off-by: M. Vefa Bicakci <m.v.b@runbox.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-08-28x86/intel: Aggregate big core mobile namingPeter Zijlstra
Currently big core mobile chips have either: - _L - _ULT - _MOBILE Make it uniformly: _L. for i in `git grep -l "\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*_\(MOBILE\|ULT\)"` do sed -i -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*\)_\(MOBILE\|ULT\)/\1_L/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Tony Luck <tony.luck@intel.com> Cc: x86@kernel.org Cc: Dave Hansen <dave.hansen@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190827195122.568978530@infradead.org
2019-08-28x86/intel: Aggregate big core client namingPeter Zijlstra
Currently the big core client models either have: - no OPTDIFF - _CORE - _DESKTOP Make it uniformly: 'no OPTDIFF'. for i in `git grep -l "\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*_\(CORE\|DESKTOP\)"` do sed -i -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*\)_\(CORE\|DESKTOP\)/\1/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Tony Luck <tony.luck@intel.com> Cc: x86@kernel.org Cc: Dave Hansen <dave.hansen@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190827195122.513945586@infradead.org
2019-07-25platform/x86: intel_pmc_core: Add ICL-NNPI support to PMC CoreRajneesh Bhardwaj
Ice Lake Neural Network Processor for deep learning inference a.k.a. ICL-NNPI can re-use Ice Lake Mobile regmap to enable Intel PMC Core driver on it. Cc: Darren Hart <dvhart@infradead.org> Cc: Andy Shevchenko <andy@infradead.org> Cc: platform-driver-x86@vger.kernel.org Link: https://lkml.org/lkml/2019/6/5/1034 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-07-08platform/x86: intel_pmc_core: Attach using APCI HID "INT33A1"Rajat Jain
Most modern platforms already have the ACPI device "INT33A1" that could be used to attach to the driver. Switch the driver to using that and thus make the intel_pmc_core.c a pure platform_driver. Some of the legacy platforms though, may still not have this ACPI device in their ACPI tables. Thus for such platforms, move the code to manually instantiate a platform_device into a new file of its own. This would instantiate the intel_pmc_core platform device and thus attach to the driver, if the ACPI device for the same ("INT33A1") is not present in a system where it should be. This was discussed here: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1966991.html Signed-off-by: Rajat Jain <rajatja@google.com> [andy: renamed to intel_pmc_core_pltdrv.c to be in align with other drivers] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-07-03platform/x86: intel_pmc_core: transform Pkg C-state residency from TSC ticks ↵Harry Pan
into microseconds Refer to the Intel SDM Vol.4, the package C-state residency counters of modern IA micro-architecture are all ticking in TSC frequency, hence we can apply simple math to transform the ticks into microseconds. i.e., residency (ms) = count / tsc_khz residency (us) = count / tsc_khz * 1000 This also aligns to other sysfs debug entries of residency counter in the same metric in microseconds, benefits reading and scripting. v2: restore the accidentally deleted newline, no function change. v3: apply kernel do_div() macro to calculate division Signed-off-by: Harry Pan <harry.pan@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-17platform/x86: intel_pmc: no need to check return value of debugfs_create ↵Greg Kroah-Hartman
functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Cc: Vishwanath Somayaji <vishwanath.somayaji@intel.com> Cc: Darren Hart <dvhart@infradead.org> Cc: Andy Shevchenko <andy@infradead.org> Cc: platform-driver-x86@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-05-06platform/x86: intel_pmc_core: Allow to dump debug registers on S0ix failureRajat Jain
Add a module parameter which when enabled, will check on resume, if the last S0ix attempt was successful. If not, the driver would warn and provide helpful debug information (which gets latched during the failed suspend attempt) to debug the S0ix failure. This information is very useful to debug S0ix failures. Specially since the latched debug information will be lost (over-written) if the system attempts to go into runtime (or imminent) S0ix again after that failed suspend attempt. Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-05-06platform/x86: intel_pmc_core: Convert to a platform_driverRajat Jain
Convert the intel_pmc_core driver to a platform driver. There is no functional change to the driver, or to the way the devices are instantiated. Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-08platform/x86: intel_pmc_core: Mark local function staticGuenter Roeck
0day reports: drivers/platform/x86/intel_pmc_core.c:833:5: sparse: symbol 'quirk_xtal_ignore' was not declared. Should it be static? Mark the function static since it is indeed only called locally. Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Fixes: 238f9c11351f ("platform/x86: intel_pmc_core: Quirk to ignore XTAL shutdown") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-02-23platform/x86: intel_pmc_core: Quirk to ignore XTAL shutdownRajneesh Bhardwaj
On some platforms such as HP Elite-x2-1013-g3, the platform BIOS enforces XTAL to remain off before S0ix state can be achieved. This may not be optimum when we want to enable use cases like Low Power Audio, Wake on Voice etc which always need 24mhz clock. This introduces a new quirk to allow S0ix entry when all other conditions except for XTAL clock are good on a given platform. The extra power consumed by XTAL clock is about 2mw but it saves much more platform power compared to the system that remains in just PC10. Link: https://bit.ly/2UmnrFf Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201579 Tested-by: "David E. Box" <david.e.box@linux.intel.com> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
2019-02-23platform/x86: intel_pmc_core: Add Package cstates residency infoRajneesh Bhardwaj
This patch introduces a new debugfs entry to read current Package cstate residency counters. A similar variant of this patch was discussed earlier "https://patchwork.kernel.org/patch/9908563/" but didn't make it into mainline for various reasons. Current version only adds debugfs entry which is quite useful for S0ix debug but excludes the exported API that was there in initial version. Though there are tools like turbostat and socwatch which can also show this info but sometimes its more practical to have it here as it's hard to switch between various tools for S0ix debug when pmc_core driver is the primary debug tool. Internal and external customers have requested for this patch to be included in the PMC driver on many occasions and Google Chrome OS team has already included it in their builds. This becomes handy when requesting logs from external customers who may not always have above mentioned tools in their integrated kernel builds. Package cstate residency MSRs provide useful debug information about system idle states. In idle states system must enter deeper Package cstates. Package cstates depend not only on Core cstates but also on various IP block's power gating status and LTR values. For Intel Core SoCs Package C10 entry is a must for deeper sleep states such as S0ix. "Suspend-to-idle" should ideally take this path: PC0 -> PC10 -> S0ix. For S0ix debug, its logical to check for Package C10 residency first if for some reason system fails to enter S0ix. Please refer to this link for MSR details: https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf Usage: cat /sys/kernel/debug/pmc_core/package_cstate_show Package C2 : 0xec2e21735f Package C3 : 0xc30113ba4 Package C6 : 0x9ef4be15c5 Package C7 : 0x1e011904 Package C8 : 0x3c5653cfe5a Package C9 : 0x0 Package C10 : 0x16fff4289 Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Len Brown <len.brown@intel.com> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-and-tested-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
2019-02-23platform/x86: intel_pmc_core: Add ICL platform supportRajneesh Bhardwaj
Icelake can resue most of the CNL PCH IPs as they are mostly similar. This patch enables the PMC Core driver for ICL family. It also addresses few other minor issues like upper case conversions and some tab alignments. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-and-tested-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
2019-02-23platform/x86: intel_pmc_core: Convert to INTEL_CPU_FAM6 macroRajneesh Bhardwaj
INTEL_CPU_FAM6() macro provides better abstraction and reduces code size so use it instead of custom grown ICPU(). Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
2019-02-23platform/x86: intel_pmc_core: Avoid a u32 overflowRajat Jain
The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register. The pmc_core_adjust_slp_s0_step() could overflow the u32 value while returning it after adjusting the step. Thus change to u64, this is already accounted for in debugfs attribute (that wants to output a 64 bit value). Signed-off-by: Rajat Jain <rajatja@google.com> Acked-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
2019-02-21platform/x86: intel_pmc_core: Include Reserved IP for LTRRajneesh Bhardwaj
Recently introduced commit "platform/x86: intel_pmc_core: Show Latency Tolerance info <51337cd94d18184601ac0fb4cf1a02b8bbabc3d7> skipped the LTR from a reserved IP. Though this doesn't cause any functional issue but it is needed for the consumers of "ltr_ignore" as the index printing for "ltr_show" is missing. For example, w/o this change, a user that wants to ignore LTR from ME would do something like echo 5 > ltr_ignore but the index for ME is 6. Printing a reserved IP helps to properly calculate LTR ignore offsets. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-02-21platform/x86: intel_pmc_core: Fix file permissions for ltr_showRajneesh Bhardwaj
File permissions for ltr_show attribute should be similar to other debugfs attributes created by this driver. '0644' should be used only when there is a write operation desired such as for ltr_ignore. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Fixes: 2eb150558bb7 ("platform/x86: intel_pmc_core: Show Latency Tolerance info") Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-02-05platform/x86: intel_pmc_core: Fix PCH IP nameRajneesh Bhardwaj
For Cannonlake and Icelake, the IP name for Res_6 should be SPF i.e. South Port F. No functional change is intended other than just renaming the IP appropriately. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Fixes: 291101f6a735 ("platform/x86: intel_pmc_core: Add CannonLake PCH support") Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-02-05platform/x86: intel_pmc_core: Fix PCH IP sts readingRajneesh Bhardwaj
A previous commit "platform/x86: intel_pmc_core: Make the driver PCH family agnostic <c977b98bbef5898ed3d30b08ea67622e9e82082a>" provided better abstraction to this driver but has some fundamental issues. e.g. the following condition for (index = 0; index < pmcdev->map->ppfear_buckets && index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) is wrong because for CNL, PPFEAR_MAX_NUM_ENTRIES is hardcoded as 5 which is _wrong_ and even though ppfear_buckets is 8, the loop fails to read all eight registers needed for CNL PCH i.e. PPFEAR0 and PPFEAR1. This patch refactors the pfear show logic to correctly read PCH IP power gating status for Cannonlake and beyond. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Fixes: c977b98bbef5 ("platform/x86: intel_pmc_core: Make the driver PCH family agnostic") Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-02-05platform/x86: intel_pmc_core: Handle CFL regmap properlyRajneesh Bhardwaj
Only Coffeelake should use Cannonlake regmap other than Cannonlake platform. This allows Coffeelake special handling only when there is no matching PCI device and default reg map selected as per CPUID is for Sunrisepoint PCH. This change is needed to enable support for newer SoCs such as Icelake. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Fixes: 661405bd817b ("platform/x86: intel_pmc_core: Special case for Coffeelake") Acked-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-12-10platform/x86: intel_pmc_core: convert to DEFINE_SHOW_ATTRIBUTEYangtao Li
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-10platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTRRajneesh Bhardwaj
The LTR values follow PCIE LTR encoding format and can be decoded as per https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf This adds support to translate the raw LTR values as read from the PMC to meaningful values in nanosecond units of time. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-10platform/x86: intel_pmc_core: Fix LTR IGNORE Max offsetRajneesh Bhardwaj
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint PCH so make the LTR ignore platform specific. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-10platform/x86: intel_pmc_core: Show Latency Tolerance infoRajneesh Bhardwaj
This adds support to show the Latency Tolerance Reporting for the IPs on the PCH as reported by the PMC. The format shown here is raw LTR data payload that can further be decoded as per the PCI specification. This also fixes some minor alignment issues in the header file by removing spaces and converting to tabs at some places. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-09-27platform/x86: intel_pmc: Convert to use SPDX identifierAndy Shevchenko
Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. While here, correct MODULE_LICENSE() string to be aligned with license text. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-02platform/x86: intel_pmc_core: Add CNP SLPS0 debug registersBox, David E
Adds debugfs access to registers in the Cannon Point PCH PMC that are useful for debugging #SLP_S0 signal assertion and other low power relate activities. Device pm states are latched in these registers whenever the package enters C10 and can be read from slp_s0_debug_status. The pm states may also be latched by writing 1 to slp_s0_dbg_latch which will immediately capture the current state on the next read of slp_s0_debug_status. Signed-off-by: Box, David E <david.e.box@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-02-04platform/x86: intel_pmc_core: Special case for CoffeelakeRajneesh Bhardwaj
Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in this case PMC register details from Cannonlake PCH must be used. In order to identify whether the given platform is Coffeelake, scan for the Sunrisepoint PMC PCI Id. KBL CPUID SPT PCIID ------------------------------------ KBL | Y | Y | ------------------------------------ CFL | Y | N | ------------------------------------ Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-02-04platform/x86: intel_pmc_core: Add CannonLake PCH supportRajneesh Bhardwaj
This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-02-04platform/x86: intel_pmc_core: Read base address from LPITSrinivas Pandruvada
Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-02-01platform/x86: intel_pmc_core: Remove unused header fileRajneesh Bhardwaj
Recently sent patch 'platform/x86: intel_pmc_core: Remove unused EXPORTED API' missed to remove the header file 'arch/x86/include/asm/pmc_core.h' which was solely used to declare the EXPORTED API 'intel_pmc_slp_s0_counter_read'. This patch provides the errata fix for the same. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-29platform/x86: intel_pmc_core: Convert to ICPU macroRajneesh Bhardwaj
Use ICPU macro to refactor code related to x86_cpu_id for better readability. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-29platform/x86: intel_pmc_core: Substitute PCI with CPUID enumerationSrinivas Pandruvada
The Only use of PCI device enumeration here is to get the PMC base address which is a fixed value i.e. 0xFE000000. On some platforms this can be read through a non standard PCI BAR. But after Kabylake, PMC is not exposed as a PCI device anymore. There are other non standard methods like ACPI LPIT which can also be used for obtaining this value. For simplicity, this value can be hardcoded as it won't change. Since we don't have a PMC PCI device on any platform after Kabylake, this creates a foundation for future SoC support. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-29platform/x86: intel_pmc_core: Refactor debugfs entriesRajneesh Bhardwaj
When on a platform if we can't show MPHY and PLL status, don't even bother to create a debugfs entry as it will fail anyway. In fact unless OEM builds a special BIOS for test, it will fail on every production system. This will help to add future platform support where we can't support these entries. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-16platform/x86: intel_pmc_core: Fix file permission warningsRajneesh Bhardwaj
Symbolic permissions 'S_IRUGO' are not preferred. This patch changes the debugfs files to use octal permissions '0644' or '0444' as needed by the attribute. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-16platform/x86: intel_pmc_core: Change driver to a moduleSrinivas Pandruvada
Allow the driver to be a module since builtin_pci_driver funtionality is no longer needed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-16platform/x86: intel_pmc_core: Remove unused EXPORTED APIRajneesh Bhardwaj
Though ChromeOs uses the exported API as part of their S0ix failsafe mechanism, there is no active consumer of this API in upstream kernel. We can revisit this when ChromeOs kernel team is able to get their S0ix failsafe framework in mainline. Cc: Derek Basehore <dbasehore@chromium.org> Cc: Rajat Jain <rajatja@google.com> Link: https://patchwork.kernel.org/patch/9831229/ Suggested-by: Andriy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-08-13platform/x86: intel_pmc_core: Make the driver PCH family agnosticSrinivas Pandruvada
Although this driver did pretty good job in abstracting PCH specific interfaces, but still there are some loose ends. For example SLP_S0 counter (for reading SLP_S0 residency), PM config offset (for checking permissions to read XRAM) and PPFEAR offset (for reading IP status) is still hardcoded for a specific family of PCH. This change extended the struct pmc_reg_map to allow per family configuration of offsets and bits. No functional change is expected with this change. This change allows seamless additions to new PCH and create a baseline for other platform specific extensions. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-14platform/x86: intel_pmc_core: fix out-of-bounds accesses on stackAndrey Ryabinin
pmc_core_mtpmc_link_status() an pmc_core_check_read_lock_bit() use test_bit() on local 32-bit variable. This causes out-of-bounds access since test_bit() expects object at least of 'unsigned long' size: BUG: KASAN: stack-out-of-bounds in pmc_core_probe+0x3aa/0x3b0 Call Trace: __asan_report_load_n_noabort+0x5c/0x80 pmc_core_probe+0x3aa/0x3b0 local_pci_probe+0xf9/0x1e0 pci_device_probe+0x27b/0x350 driver_probe_device+0x419/0x830 __driver_attach+0x15f/0x1d0 bus_for_each_dev+0x129/0x1d0 driver_attach+0x42/0x70 bus_add_driver+0x385/0x690 driver_register+0x1a9/0x3d0 __pci_register_driver+0x1a2/0x290 intel_pmc_core_driver_init+0x19/0x1b do_one_initcall+0x12e/0x280 kernel_init_freeable+0x57c/0x623 kernel_init+0x13/0x140 ret_from_fork+0x2e/0x40 Fix this by open coding bit test. While at it, also refactor this code a little bit. Fixes: 173943b3dae5 ("platform/x86: intel_pmc_core: ModPhy core lanes pg status") Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com> [andy: reverted not related changes, used BIT() macro] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: Add KBL CPUID supportRajneesh Bhardwaj
This patch adds Kabylake CPU support for pmc_core driver. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: Add LTR IGNORE debug featureRajneesh Bhardwaj
SPT LTR_IGN register provides a means to make the PMC ignore the LTR values reported by the individual PCH devices. echo <IP Offset> > /sys/kernel/debug/pmc_core/ltr_ignore. When a particular IP Offset bit is set the PMC will ignore the LTR value reported by the corresponding IP when the PMC performs the latency coalescing. IP Offset IP Name 0 SPA 1 SPB 2 SATA 3 GBE 4 XHCI 5 RSVD 6 ME 7 EVA 8 SPC 9 Azalia/ADSP 10 RSVD 11 LPSS 12 SPD 13 SPE 14 Camera 15 ESPI 16 SCC 17 ISH Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> [dvhart: pmc_core_ltr_ignore_write local declaration order cleanup] Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: Add MPHY PLL clock gating statusRajneesh Bhardwaj
ModPhy Common lanes can provide the clock gating status for the important system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL and MIPI PLL. On SPT, in addition to the crystal oscillator clock, the 100Mhz Gen2 USB3PCI2 PLL clock is used as the PLL reference clock and Gen2 PLL idling is a necessary condition for the platform to go into low power states like PC10 and S0ix. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: ModPhy core lanes pg statusRajneesh Bhardwaj
The PCH implements a number of High Speed I/O (HSIO) lanes that are split between PCIe*, USB 3.0, SATA, GbE, USB OTG and SSIC. This patch shows the current power gating status of the available ModPhy Core lanes. This is done by sending a message to the PMC (MTPMC) that contains the XRAM register offset for the MPHY_CORE_STS_0 and MPHY_CORE_STS_1 and then by reading the response sent by the PMC (MFPMC). While enabling low power modes we often encounter situations when the ModPhy lanes are not power gated and it becomes hard to debug which lane is active and which is not in the absence of an external hardware debugger (JTAG/ITP). This patch eliminates the dependency on an external hardware debugger for reading the ModPhy Lanes power gating status. This patch requires PMC_READ_DISABLE setting to be disabled in the platform bios. cat /sys/kernel/debug/pmc_core/mphy_lanes_power_gating_status Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: Add PCH IP Power Gating StatusRajneesh Bhardwaj
This patch adds the support for reading the power gating status of various devices present on Sunrise Point PCH. This is intended to be used for debugging purpose while tuning the platform for power optimizations and also to understand which devices (on PCH) are blocking the system to enter a low power state. Power Management Controller on Sunrise Point PCH provides access to "PGD PFET Enable Ack Status Registers (ppfear)". This patch reads and decodes this register and dumps the output in formatted manner showing various devices present on the PCH and their "Power Gating" status. Further documentation can be found in Intel 7th Gen Core family mobile u/y processor io datasheet volume 2. Sample output (stripped and not in order): cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status PMC State: Not Power gated OPI-DMI State: Not Power gated XHCI State: Power gated LPSS State: Power gated CSME_PSF State: Not power gated Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-12-13platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg lenRajneesh Bhardwaj
On Sunrise Point PCH, the Power Management Controller provides 4K bytes of memory space for various power management and debug registers. This fix is needed to access power management & debug registers that are mapped at a higher offset. Also, this provides a fix for correctly masking the PWRMBASE as the initial bits (0-11) are reserved. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-10-12platform/x86: intel_pmc_core: avoid boot time warning for !CONFIG_DEBUGFS_FSArnd Bergmann
While looking at a patch that introduced a compile-time warning "‘pmc_core_dev_state_get’ defined but not used" (I sent a patch for debugfs to fix it), I noticed that the same patch caused it in intel_pmc_core also introduced a bogus run-time warning: "PMC Core: debugfs register failed". The problem is the IS_ERR_OR_NULL() check that as usual gets things wrong: when CONFIG_DEBUGFS_FS is disabled, debugfs_create_dir() fails with an error code, and we don't need to warn about it, unlike the case in which it returns NULL. This reverts the driver to the previous state of not warning about CONFIG_DEBUGFS_FS being disabled. I chose not to restore the driver to making a runtime error in debugfs fatal in pmc_core_probe(). Fixes: df2294fb6428 ("intel_pmc_core: Convert to DEFINE_DEBUGFS_ATTRIBUTE") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
2016-07-26Merge tag 'platform-drivers-x86-v4.8-1' of ↵Linus Torvalds
git://git.infradead.org/users/dvhart/linux-platform-drivers-x86 Pull x8 platform driver updates from Darren Hart: "Several new quirks and tweaks for new platforms to existing laptop drivers. A new ACPI virtual power button driver, similar to the intel-hid driver. A rework of the dell keymap, using a single sparse keymap for all machines. A few fixes and cleanups. Summary: intel-vbtn: - new driver for Intel Virtual Button intel_pmc_core: - Convert to DEFINE_DEBUGFS_ATTRIBUTE fujitsu-laptop: - Rework brightness of eco led asus-wmi: - Add quirk_no_rfkill_wapf4 for the Asus X456UA - Add quirk_no_rfkill_wapf4 for the Asus X456UF - Add quirk_no_rfkill for the Asus Z550MA - Add quirk_no_rfkill for the Asus U303LB - Add quirk_no_rfkill for the Asus N552VW - Create quirk for airplane_mode LED - Add ambient light sensor toggle key asus-wireless: - Toggle airplane mode LED intel_telemetry: - Remove Monitor MWAIT feature dependency intel-hid: - Remove duplicated acpi_remove_notify_handler fujitsu-laptop: - Add support for eco LED - Support touchpad toggle hotkey on Skylake-based models - Remove unused macros - Use module name in debug messages hp-wmi: - Fix wifi cannot be hard-unblocked toshiba_acpi: - Bump driver version and update copyright year - Remove the position sysfs entry - Add IIO interface for accelerometer axis data dell-wmi: - Add a WMI event code for display on/off - Generate one sparse keymap for all machines - Add information about other WMI event codes - Sort WMI event codes and update comments - Ignore WMI event code 0xe045" * tag 'platform-drivers-x86-v4.8-1' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86: (26 commits) intel-vbtn: new driver for Intel Virtual Button intel_pmc_core: Convert to DEFINE_DEBUGFS_ATTRIBUTE fujitsu-laptop: Rework brightness of eco led asus-wmi: Add quirk_no_rfkill_wapf4 for the Asus X456UA asus-wmi: Add quirk_no_rfkill_wapf4 for the Asus X456UF asus-wmi: Add quirk_no_rfkill for the Asus Z550MA asus-wmi: Add quirk_no_rfkill for the Asus U303LB asus-wmi: Add quirk_no_rfkill for the Asus N552VW asus-wmi: Create quirk for airplane_mode LED asus-wireless: Toggle airplane mode LED intel_telemetry: Remove Monitor MWAIT feature dependency intel-hid: Remove duplicated acpi_remove_notify_handler asus-wmi: Add ambient light sensor toggle key fujitsu-laptop: Add support for eco LED fujitsu-laptop: Support touchpad toggle hotkey on Skylake-based models fujitsu-laptop: Remove unused macros fujitsu-laptop: Use module name in debug messages hp-wmi: Fix wifi cannot be hard-unblocked toshiba_acpi: Bump driver version and update copyright year toshiba_acpi: Remove the position sysfs entry ...
2016-07-06intel_pmc_core: Convert to DEFINE_DEBUGFS_ATTRIBUTEAndy Shevchenko
Refactor the code to use the recently introduced DEFINE_DEBUGFS_ATTRIBUTE() macro to eliminate boilerplate code. Make the absence of DEBUG_FS a non-fatal error. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
generated by cgit (git 2.34.1) at 2024-06-30 20:22:23 +0000