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path: root/drivers/soc/qcom
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2022-11-09soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeupMaulik Shah
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Save base address of drvMaulik Shah
Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Attach RSC to cluster PM domainLina Iyer
RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org
2022-11-07soc: qcom: apr: Add check for idr_alloc and of_property_read_string_indexJiasheng Jiang
As idr_alloc() and of_property_read_string_index() can return negative numbers, it should be better to check the return value and deal with the exception. Therefore, it should be better to use goto statement to stop and return error. Fixes: 6adba21eb434 ("soc: qcom: Add APR bus driver") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107014403.3606-1-jiasheng@iscas.ac.cn
2022-11-07soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id tableMelody Olvera
Add SoC ID table entries for the QDU1000 and QRU1000 platforms and their variants. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-6-quic_molvera@quicinc.com
2022-11-07soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domainsMelody Olvera
Add the power domains exposed by RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-4-quic_molvera@quicinc.com
2022-11-05soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PMAngeloGioacchino Del Regno
Implement the support for SAW v2.3, used in at least MSM8976, MSM8956 and APQ variants and while at it also add the configuration for the MSM8976's little (a53) and big (a72) clusters cache power management. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Marijn: reorder struct definitions to follow high-to-low order] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104133452.131227-3-angelogioacchino.delregno@collabora.com
2022-11-05soc: qcom: llcc: make irq truly optionalLuca Weiss
The function platform_get_irq prints an error message into the kernel log when the irq isn't found. Since the interrupt is actually optional and not provided by some SoCs, use platform_get_irq_optional which does not print an error message. Fixes: c081f3060fab ("soc: qcom: Add support to register LLCC EDAC driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104153041.412020-1-luca.weiss@fairphone.com
2022-11-05soc: qcom: spm: Add MSM8939 SPM register dataVincent Knecht
Add SPM register information and initialization values for QCOM MSM8939 SoC. Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221019171004.1080911-2-vincent.knecht@mailoo.org
2022-10-17soc: qcom: stats: Mark device as having no PM supportStephen Boyd
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221015004934.3930651-2-swboyd@chromium.org
2022-10-17soc: qcom: cmd-db: Mark device as having no PM supportStephen Boyd
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221015004934.3930651-1-swboyd@chromium.org
2022-10-17soc: qcom: pdr: Make QMI message rules constJeff Johnson
Commit ff6d365898d4 ("soc: qcom: qmi: use const for struct qmi_elem_info") allows QMI message encoding/decoding rules to be const, so do that for QCOM PDR. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914234705.28405-5-quic_jjohnson@quicinc.com
2022-10-17soc: qcom: rpmhpd: Use highest corner until sync_stateBjorn Andersson
In some cases the hardware that the bootloader has left configured depends on RPMH power domains for their operation up until the point where the related Linux device driver probes and can inherit that configuration, or power down the hardware gracefully. Unfortunately as Linux probes the releavant drivers in sequence there are periods during the Linux boot flow where either the genpd refcount will reach 0, or worse where the active performance_state votes does not meet the requirements of the state that the hardware was left in. One specific example of this is during boot of e.g. SM8150/SC8180X, where the display clock controller probes, without any particular performance state needs (to access its registers). This will drop the MMCX rail to MIN_SVS, which isn't sufficient to sustain the clock rates that the later probing MDP is configured to. This results in an unrecoverable system state. Handle both these cases by keeping the RPMH power-domais that are referenced voted for highest state, until sync_state indicates that all devices referencing the RPMH power-domain driver has been probed. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Added print for sync_state errors] Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220915205559.14574-1-quic_bjorande@quicinc.com
2022-10-17soc: qcom: smd-rpm: Add SM6375 compatibleKonrad Dybcio
Add a compatible for the SM6375 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004534.151990-2-konrad.dybcio@somainline.org
2022-10-17soc: qcom: smd-rpm: Replace zero-length array with DECLARE_FLEX_ARRAY() helperGustavo A. R. Silva
Zero-length arrays are deprecated and we are moving towards adopting C99 flexible-array members, instead. So, replace zero-length arrays declarations in anonymous union with the new DECLARE_FLEX_ARRAY() helper macro. This helper allows for flexible-array members in unions. Link: https://github.com/KSPP/linux/issues/193 Link: https://github.com/KSPP/linux/issues/224 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/YzIvNIyPhWaG2DTr@work
2022-10-17soc: qcom: rpmhpd: add sdm670 power domainsRichard Acayan
The Snapdragon 670 has similar power domains to SDM845 but no EBI power domain. Add a new array for them to avoid requesting a power domain which is unsupported by the hardware. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221004221130.14076-3-mailingradian@gmail.com
2022-10-17soc: qcom: socinfo: create soc_id table from bindingsKrzysztof Kozlowski
The Qualcomm SoC ID values are encoded in few places: DTS files, Devicetree bindings (both used by some of Qualcomm bootloaders or tools) and in soc_id table of socinfo driver. Do not duplicate the actual values in the last one but use the constants from the bindings. Tested by comparing output object file (exactly the same). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830065744.161163-3-krzysztof.kozlowski@linaro.org
2022-10-17soc: qcom: move from strlcpy with unused retval to strscpyWolfram Sang
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> [bjorn: Only applied qcom-part of patch] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818210106.7349-1-wsa+renesas@sang-engineering.com
2022-09-13soc: qcom: rpmpd: Add SM6375 supportKonrad Dybcio
Add support for RPMPDs on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220716193201.455728-2-konrad.dybcio@somainline.org
2022-09-05soc: qcom: icc-bwmon: force clear counter/irq registersRajendra Nayak
In some SoCs we have to force clear the counter/irq clear registers as they are not self clearing after they are written into. sc7280 seems to be one such SoC, handle this with a quirk flag. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220902043511.17130-4-quic_rjendra@quicinc.com
2022-09-05soc: qcom: icc-bwmon: add support for sc7280 LLCC BWMONRajendra Nayak
Add support for sc7280 BWMON instance measuring traffic between LLCC and memory with the v5 register layout. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220902043511.17130-3-quic_rjendra@quicinc.com
2022-08-29Merge tag '20220825043859.30066-3-manivannan.sadhasivam@linaro.org' into ↵Bjorn Andersson
drivers-for-6.1 v6.0-rc1 + 20220825043859.30066-2-manivannan.sadhasivam@linaro.org + 20220825043859.30066-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2022-08-29soc: qcom: llcc: Pass LLCC version based register offsets to EDAC driverManivannan Sadhasivam
The LLCC EDAC register offsets varies between each SoCs. Until now, the EDAC driver used the hardcoded register offsets. But this caused crash on SM8450 SoC where the register offsets has been changed. So to avoid this crash and also to make it easy to accommodate changes for new SoCs, let's pass the LLCC version specific register offsets to the EDAC driver. Currently, two set of offsets are used. One is starting from LLCC version v1.0.0 used by all SoCs other than SM8450. For SM8450, LLCC version starting from v2.1.0 is used. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220825043859.30066-3-manivannan.sadhasivam@linaro.org
2022-08-29soc: qcom: llcc: Rename reg_offset structs to reflect LLCC versionManivannan Sadhasivam
The register offsets used by the LLCC block retains its layout for multiple versions. For instance, starting from version v1.0.0 to v2.0.1 the offsets are same. And starting from v2.1.0, the offsets changed. But the current reg_offset naming convention is confusing. So to reflect this change correctly in driver, let's encode the start version from which the offsets got changed in reg_offset struct name. This will be llcc_v1_reg_offset for v1.0.0 and llcc_v2_1_reg_offset for v2.1.0. This will allow multiple SoCs to use the same reg_offset clearly. And in the future if the offsets got changed again, then that specific version could be encoded in the struct name. Suggested-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220825043859.30066-2-manivannan.sadhasivam@linaro.org
2022-08-29soc: qcom: qmi: use const for struct qmi_elem_infoJeff Johnson
Currently all usage of struct qmi_elem_info, which is used to define the QMI message encoding/decoding rules, does not use const. This prevents clients from registering const arrays. Since these arrays are always pre-defined, they should be const, so add the const qualifier to all places in the QMI interface where struct qmi_elem_info is used. Once this patch is in place, clients can independently update their pre-defined arrays to be const, as demonstrated in the QMI sample code. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220822153435.7856-1-quic_jjohnson@quicinc.com
2022-08-29soc: qcom: icc-bwmon: remove redundant ret variableJinpeng Cui
Return value from devm_regmap_field_bulk_alloc() directly instead of taking this in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Jinpeng Cui <cui.jinpeng2@zte.com.cn> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220823133620.211902-1-cui.jinpeng2@zte.com.cn
2022-08-29soc: qcom: stats: Add SDM845 stats config and compatibleAbel Vesa
SDM845 is a special case compared to the other platforms that use RPMh stats, since it only has 2 stats (aosd and cxsd), while the others have a 3rd one (ddr). So lets add dedicated stats config and compatible for SDM845 to make the driver aware of this num_records difference. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812101240.1869605-2-abel.vesa@linaro.org
2022-08-29soc: qcom: Make QCOM_RPMPD depend on OFYueHaibing
WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS_OF Depends on [n]: PM_GENERIC_DOMAINS [=y] && OF [=n] Selected by [m]: - QCOM_RPMPD [=m] && PM [=y] && QCOM_SMD_RPM [=m] PM_GENERIC_DOMAINS_OF depends on OF, so QCOM_RPMPD also depends on it. Fixes: 7d0221fb5912 ("soc/qcom: Make QCOM_RPMPD select PM_GENERIC_DOMAINS/_OF") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220820113202.23940-1-yuehaibing@huawei.com
2022-08-18soc: qcom: socinfo: Add PM6125 IDKonrad Dybcio
PM6125 has the ID 45. Add it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220723100225.92053-2-konrad.dybcio@somainline.org
2022-08-18soc: qcom: socinfo: Add an ID for SM6375Konrad Dybcio
Add an ID for SM6375, also known as BLAIR. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220723100225.92053-1-konrad.dybcio@somainline.org
2022-08-18soc: qcom: smem_state: Add refcounting for the 'state->of_node'Liang He
In qcom_smem_state_register() and qcom_smem_state_release(), we should better use of_node_get() and of_node_put() for the reference creation and destruction of 'device_node'. Fixes: 9460ae2ff308 ("soc: qcom: Introduce common SMEM state machine code") Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220721135217.1301039-2-windhl@126.com
2022-08-18soc: qcom: smsm: Fix refcount leak bugs in qcom_smsm_probe()Liang He
There are two refcount leak bugs in qcom_smsm_probe(): (1) The 'local_node' is escaped out from for_each_child_of_node() as the break of iteration, we should call of_node_put() for it in error path or when it is not used anymore. (2) The 'node' is escaped out from for_each_available_child_of_node() as the 'goto', we should call of_node_put() for it in goto target. Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220721135217.1301039-1-windhl@126.com
2022-08-18soc: qcom: icc-bwmon: add support for SDM845 LLCC BWMONKrzysztof Kozlowski
The SDM845 comes with few instances of Bandwidth Monitor. The already supported one monitors traffic between CPU and Last Level Cache Controller (LLCC) and in downstream sources is called BWMON v4 (or v4 of register layout). SDM845 also has also BWMON instance measuring traffic between LLCC and memory with different register layout: called v5. Add support for this "LLCC" BWMON. Differences against existing v4 one: 1. No global interrupts. 2. Different register layout. 3. Different shift of interrupt fields. 4. Smaller sampling window. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-10-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: add per-variant quirksKrzysztof Kozlowski
BWMON v5 lacks global interrupt registers. Other BWMON versions differ as well, so add quirks for easier customization of code flow. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-9-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: use regmap and prepare for BWMON v5Krzysztof Kozlowski
Refactor the code to prepare it for supporting BWMON v5 which comes with different register layout by: 1. Adding use of MMIO regmap and regmap fields which allows to keep one code logic with different register maps. 2. The "clear" type registers do not allow reading, therefore regmap requires using cache with default values. 3. regmap has an effect of introducing barriers after each readl/writel, which should negligible effect as only few writes were relaxed. 4. Additionally usage of regmap fields removes need of shifting the register values. 5. Add "V4" prefix to names of all defines with register addresses (so BWMON_V4_xxx) to differentiate it from V5. The actual register values are shared so keep their naming. 6. While changing the defines, pad register addresses to three digits for readability. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-8-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: store count unit per variantKrzysztof Kozlowski
Versions v4 and v5 of BWMON on SDM845 use different unit count, so allow easier variant customization by storing its value in struct icc_bwmon_data. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-7-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: clear all registers on initKrzysztof Kozlowski
The hardware programming guide recommends to clear all registers on first initialization, through separate field in BWMON_CLEAR register. This makes sense in general but especially if driver is rebound to avoid spurious/early interrupts. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-6-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: store reference to variant data in containerKrzysztof Kozlowski
Instead of copying pieces of variant-specific data (struct icc_bwmon_data) into the state container (struct icc_bwmon), just store a pointer to it. This simplifies a bit the code and allows later to grow easily the variant-specific data for new BWMON v5. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-5-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: drop unused registersKrzysztof Kozlowski
BWMON_GLOBAL_IRQ_STATUS and BWMON_ZONE_COUNT defines are not used. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-4-krzysztof.kozlowski@linaro.org
2022-08-18soc: qcom: icc-bwmon: re-use IRQ enable/clear defineKrzysztof Kozlowski
The interrupt enable, status and clear registers have the same layout, so BWMON_GLOBAL_IRQ_ENABLE_ENABLE define can be used also for clearing IRQ, instead of hard-coded value. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220728113748.170548-3-krzysztof.kozlowski@linaro.org
2022-08-05Merge tag 'asm-generic-6.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "There are three independent sets of changes: - Sai Prakash Ranjan adds tracing support to the asm-generic version of the MMIO accessors, which is intended to help understand problems with device drivers and has been part of Qualcomm's vendor kernels for many years - A patch from Sebastian Siewior to rework the handling of IRQ stacks in softirqs across architectures, which is needed for enabling PREEMPT_RT - The last patch to remove the CONFIG_VIRT_TO_BUS option and some of the code behind that, after the last users of this old interface made it in through the netdev, scsi, media and staging trees" * tag 'asm-generic-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: uapi: asm-generic: fcntl: Fix typo 'the the' in comment arch/*/: remove CONFIG_VIRT_TO_BUS soc: qcom: geni: Disable MMIO tracing for GENI SE serial: qcom_geni_serial: Disable MMIO tracing for geni serial asm-generic/io: Add logging support for MMIO accessors KVM: arm64: Add a flag to disable MMIO trace for nVHE KVM lib: Add register read/write tracing support drm/meson: Fix overflow implicit truncation warnings irqchip/tegra: Fix overflow implicit truncation warnings coresight: etm4x: Use asm-generic IO memory barriers arm64: io: Use asm-generic high level MMIO accessors arch/*: Disable softirq stacks on PREEMPT_RT.
2022-08-02Merge tag 'arm-drivers-6.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC drivers from Arnd Bergmann: "The SoC driver updates contain changes to improve support for additional SoC variants, as well as cleanups an minor bugfixes in a number of existing drivers. Notable updates this time include: - Support for Qualcomm MSM8909 (Snapdragon 210) in various drivers - Updates for interconnect drivers on Qualcomm Snapdragon - A new driver support for NMI interrupts on Fujitsu A64fx - A rework of Broadcom BCMBCA Kconfig dependencies - Improved support for BCM2711 (Raspberry Pi 4) power management to allow the use of the V3D GPU - Cleanups to the NXP guts driver - Arm SCMI firmware driver updates to add tracing support, and use the firmware interfaces for system power control and for power capping" * tag 'arm-drivers-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (125 commits) soc: a64fx-diag: disable modular build dt-bindings: soc: qcom: qcom,smd-rpm: add power-controller dt-bindings: soc: qcom: aoss: document qcom,sm8450-aoss-qmp dt-bindings: soc: qcom,rpmh-rsc: simplify qcom,tcs-config ARM: mach-qcom: Add support for MSM8909 dt-bindings: arm: cpus: Document "qcom,msm8909-smp" enable-method soc: qcom: spm: Add CPU data for MSM8909 dt-bindings: soc: qcom: spm: Add MSM8909 CPU compatible soc: qcom: rpmpd: Add compatible for MSM8909 dt-bindings: power: qcom-rpmpd: Add MSM8909 power domains soc: qcom: smd-rpm: Add compatible for MSM8909 dt-bindings: soc: qcom: smd-rpm: Add MSM8909 soc: qcom: icc-bwmon: Remove unnecessary print function dev_err() soc: fujitsu: Add A64FX diagnostic interrupt driver soc: qcom: socinfo: Fix the id of SA8540P SoC soc: qcom: Make QCOM_RPMPD depend on PM tty: serial: bcm63xx: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA spi: bcm63xx-hsspi: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA clk: bcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA hwrng: bcm2835: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA ...
2022-07-18soc: qcom: spm: Add CPU data for MSM8909Stephan Gerhold
Given the lack of public documentation for the SPM, the configuration data is taken without modification from Qualcomm's msm-3.10 release [1]. It is pretty much identical to the one for MSM8916, except that 0x3B is missing in the sequence for standalone power collapse for some reason. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.3-00910-8x09.0/arch/arm/boot/dts/qcom/msm8909-pm8909-pm.dtsi Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705143523.3390944-7-stephan.gerhold@kernkonzept.com
2022-07-18soc: qcom: rpmpd: Add compatible for MSM8909Stephan Gerhold
MSM8909 has the same power domains as MSM8916, so just define another compatible for the existing definition. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705143523.3390944-5-stephan.gerhold@kernkonzept.com
2022-07-18soc: qcom: smd-rpm: Add compatible for MSM8909Stephan Gerhold
Add the new "qcom,rpm-msm8909" compatible to the driver so the interface to the Resource Power Manager (RPM) is initialized correctly on MSM8909. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705143523.3390944-3-stephan.gerhold@kernkonzept.com
2022-07-18soc: qcom: icc-bwmon: Remove unnecessary print function dev_err()Yang Li
Eliminate the follow coccicheck warning: ./drivers/soc/qcom/icc-bwmon.c:349:2-9: line 349 is redundant because platform_get_irq() already prints an error Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220714075532.104665-1-yang.lee@linux.alibaba.com
2022-07-16soc: qcom: socinfo: Fix the id of SA8540P SoCParikshit Pareek
Change the id of SA8540P to its correct value, i.e., 461. Also, map the id 460 to its correct values, i.e. SA8295P. Fixes: 76ee15ae1b13 ("soc: qcom: socinfo: Add some more PMICs and SoCs") Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com> Reviewed-by: Eric Chanudet <echanude@redhat.com> Tested-by: Eric Chanudet <echanude@redhat.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220711083957.12091-1-quic_ppareek@quicinc.com
2022-07-16soc: qcom: Make QCOM_RPMPD depend on PMKonrad Dybcio
QCOM_RPMPD requires PM_GENERIC_DOMAINS/_OF, which in turns requires CONFIG_PM. I forgot about the latter in my earlier patch (it's still in -next as of the time of committing, hence no Fixes: tag). Fix it. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220707212158.32684-1-konrad.dybcio@somainline.org
2022-07-06soc: qcom: icc-bwmon: Add bandwidth monitoring driverKrzysztof Kozlowski
Bandwidth monitoring (BWMON) sits between various subsytems like CPU, GPU, Last Level caches and memory subsystem. The BWMON can be configured to monitor the data throuhput between memory and other subsytems. The throughput is measured within specified sampling window and is used to vote for corresponding interconnect bandwidth. Current implementation brings support for BWMON v4, used for example on SDM845 to measure bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. The driver was tested on SDM845. Co-developed-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704121730.127925-3-krzysztof.kozlowski@linaro.org
2022-07-05soc/qcom: Make QCOM_RPMPD select PM_GENERIC_DOMAINS/_OFKonrad Dybcio
The driver uses generic genpd OF APIs and with a very minimal config where nothing else selects them, this driver will not probe, as of_genpd_add_provider_onecell will return -EOPNOTSUPP. Make sure to select these in Kconfig to prevent that. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701073700.17124-1-konrad.dybcio@somainline.org
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