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path: root/drivers/soc/ti/k3-ringacc.c
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2020-09-11soc: ti: k3: ringacc: add am65x sr2.0 supportGrygorii Strashko
The AM65x SR2.0 Ringacc has fixed errata i2023 "RINGACC, UDMA: RINGACC and UDMA Ring State Interoperability Issue after Channel Teardown". This errata also fixed for J271E SoC. Use SOC bus data for K3 SoC identification and enable i2023 errate w/a only for the AM65x SR1.0. This also makes obsolete "ti,dma-ring-reset-quirk" DT property. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3: fix semicolon.cocci warningskernel test robot
drivers/soc/ti/k3-ringacc.c:616:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 3277e8aa2504 ("soc: ti: k3: add navss ringacc driver") CC: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: kernel test robot <lkp@intel.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3-ringacc: fix: warn: variable dereferenced before check 'ring'Grygorii Strashko
Fix build warning in k3_ringacc_ring_cfg(): smatch warnings: drivers/soc/ti/k3-ringacc.c:562 k3_ringacc_ring_cfg() warn: variable dereferenced before check 'ring' (see line 559) 557 int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg) 558 { @559 struct k3_ringacc *ringacc = ring->parent; ^^^^^^^^^^^^ Dereference. 560 int ret = 0; 561 @562 if (!ring || !cfg) ^^^^ Check too late. Delete it? Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3-ringacc: separate soc specific initializationGrygorii Strashko
Separate SoC specific initialization and and OF mach data in preparation of adding support for more K3 SoCs Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3-ringacc: add request pair of rings api.Grygorii Strashko
Add new API k3_ringacc_request_rings_pair() to request pair of rings at once, as in the most cases Rings are used with DMA channels, which need to request pair of rings - one to feed DMA with descriptors (TX/RX FDQ) and one to receive completions (RX/TX CQ). This will allow to simplify Ringacc API users. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3-ringacc: add ring's flags to dumpGrygorii Strashko
Add struct k3_ring *ring->flags to the ring dump. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-24soc: ti: k3-ringacc: Move state tracking variables under a structPeter Ujfalusi
Move the free, occ, windex and rindex under a struct. We can use memset to zero them and it will allow a cleaner way to extend driver functionality in the future, Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-01-15soc: ti: k3: add navss ringacc driverGrygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The corresponding support of TI-SCI Ringacc module RM protocol introduced as option through DT parameters: - ti,sci: phandle on TI-SCI firmware controller DT node - ti,sci-dev-id: TI-SCI device identifier as per TI-SCI firmware spec if both parameters present - Ringacc driver will configure/free/reset Rings using TI-SCI Message Ringacc RM Protocol. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Tero Kristo <t-kristo@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>