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path: root/drivers/spi/spi-atmel.c
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2019-11-22Merge branch 'spi-5.5' into spi-nextMark Brown
2019-11-15spi: atmel: Use dma_request_chan() directly for channel requestPeter Ujfalusi
dma_request_slave_channel_reason() is: #define dma_request_slave_channel_reason(dev, name) \ dma_request_chan(dev, name) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20191113094256.1108-3-peter.ujfalusi@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: fix handling of cs_change set on non-last xferMans Rullgard
The driver does the wrong thing when cs_change is set on a non-last xfer in a message. When cs_change is set, the driver deactivates the CS and leaves it off until a later xfer again has cs_change set whereas it should be briefly toggling CS off and on again. This patch brings the behaviour of the driver back in line with the documentation and common sense. The delay of 10 us is the same as is used by the default spi_transfer_one_message() function in spi.c. [gregory: rebased on for-5.5 from spi tree] Fixes: 8090d6d1a415 ("spi: atmel: Refactor spi-atmel to use SPI framework queue") Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191018153504.4249-1-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Improve CS0 case support on AT91RM9200Gregory CLEMENT
Thanks to the recent change in this driver, it is now possible to prevent using the CS0 with GPIO during setup. It then allows to remove the special handling of this case in the cs_activate() and cs_deactivate() functions. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-8-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Improve and fix GPIO CS usageGregory CLEMENT
In the previous implementation of this driver, the index of the GPIO used as CS was linked to the offset of the CS register used to configure the transfer. With this new implementation the first CS register not used by internal CS is associated to all the GPIO CS. It allows to not be anymore limited to have only 4 CS managed, now it is possible to have in the same time until 3 internal CS and no more limit for the CS GPIO. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-7-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Remove platform data supportGregory CLEMENT
This driver is now only used through the device tree. Simplify code by explicitly depend on device tree. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-6-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Remove useless private fieldGregory CLEMENT
Since the conversion to GPIO descriptor, the GPIO used as chip select, can be directly access from the spi_device struct. So there is no need to keep the field npcs_pin. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-5-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Configure GPIO per CS instead of by controllerGregory CLEMENT
Instead of setting up the GPIO configuration for the whole controller, do it at CS level. It will allow to mix internal CS and GPIO CS, which is not possible with the current implementation. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-4-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Fix CS high supportGregory CLEMENT
Until a few years ago, this driver was only used with CS GPIO. The only exception is CS0 on AT91RM9200 which has to use internal CS. A limitation of the internal CS is that they don't support CS High. So by using the CS GPIO the CS high configuration was available except for the particular case CS0 on RM9200. When the support for the internal chip-select was added, the check of the CS high support was not updated. Due to this the driver accepts this configuration for all the SPI controller v2 (used by all SoCs excepting the AT91RM9200) whereas the hardware doesn't support it for infernal CS. This patch fixes the test to match the hardware capabilities. Fixes: 4820303480a1 ("spi: atmel: add support for the internal chip-select of the spi controller") Cc: <stable@vger.kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-3-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-18spi: atmel: Remove and fix erroneous commentsGregory CLEMENT
Since CSAAT functionality support has been added. Some comments become wrong. Fix them to match the current driver behavior. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-2-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15spi: use new `spi_transfer_delay_exec` helper where straightforwardAlexandru Ardelean
For many places in the spi drivers, using the new `spi_transfer_delay` helper is straightforward. It's just replacing: ``` if (t->delay_usecs) udelay(t->delay_usecs); ``` with `spi_transfer_delay(t)` which handles both `delay_usecs` and the new `delay` field. This change replaces in all places (in the spi drivers) where this change is simple. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20190926105147.7839-10-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15spi: core,atmel: convert `word_delay_usecs` -> `word_delay` for spi_deviceAlexandru Ardelean
This change does a conversion from the `word_delay_usecs` -> `word_delay` for the `spi_device` struct. This allows users to specify inter-word delays in other unit types (nano-seconds or clock cycles), depending on how users want. The Atmel SPI driver is the only current user of the `word_delay_usecs` field (from the `spi_device` struct). So, it needed a slight conversion to use the `word_delay` as an `spi_delay` struct. In SPI core, the only required mechanism is to update the `word_delay` information per `spi_transfer`. This requires a bit more logic than before, because it needs that both delays be converted to a common unit (nano-seconds) for comparison. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20190926105147.7839-8-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-01spi: atmel: Remove AVR32 leftoverGregory CLEMENT
AV32 support has been from the kernel a few release ago, but there was still some specific macro for this architecture in this driver. Lets remove it. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20190919154034.7489-1-gregory.clement@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-02spi: atmel: add tracing to custom .transfer_one_message callbackUwe Kleine-König
Driver specific implementations for .transfer_one_message need to call the tracing stuff themself. This is necessary to make spi tracing actually useful. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20190801204710.27309-1-uwe@kleine-koenig.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-30spi-atmel: support inter-word delayJonas Bonn
If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-09spi: atmel: Convert to use CS GPIO descriptorsLinus Walleij
This converts the Atmel SPI master driver to use GPIO descriptors for chip select handling. The Atmel driver has duplicate code to look up and initialize CS GPIOs from the device tree, so this is removed. It further has code to retrieve a CS GPIO from .controller_data but this seems to be completely unused in the kernel (legacy codepath?) so I deleted this support. It keeps track of polarity when switching the CS, but this is not needed anymore since we moved this over to the gpiolib. The local handling of the "npcs_pin" (I guess this might mean "negative polarity chip select pin") is preserved, but I strongly suspect this can be switched over to handling by the core and using the SPI_MASTER_GPIO_SS flag on the master to assure that the additional CS handling in the driver is also done. Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Radu Pirea <radu.pirea@microchip.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-09-05spi: Do not print a message if spi_controller_{suspend,resume}() failsGeert Uytterhoeven
spi_controller_{suspend,resume}() already prints an error message on failure, so there is no need to repeat this in individual drivers. Note: spi_master_{suspend,resume}() is an alias for spi_controller_{suspend,resume}(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Daniel Mack <daniel@zonque.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-03-28spi: spi-atmel: Use correct enum for DMA transfer directionStefan Agner
Use enum dma_transfer_direction as required by the functions dmaengine_prep_slave_(sg|single)() instead of enum dma_data_direction. This won't change behavior in practice as the enum values are equivalent. This fixes two warnings when building with clang: drivers/spi/spi-atmel.c:771:12: warning: implicit conversion from enumeration type 'enum dma_data_direction' to different enumeration type 'enum dma_transfer_direction' [-Wenum-conversion] DMA_FROM_DEVICE, ^~~~~~~~~~~~~~~ ... Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-02-27spi: atmel: init FIFOs before spi enableEugen Hristev
The datasheet recommends initializing FIFOs before SPI enable. If we do not do it like this, there may be a strange behavior. We noticed that DMA does not work properly with FIFOs if we do not clear them beforehand or enable them before SPIEN. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2018-01-05spi: atmel: Implements transfers with bounce bufferRadu Pirea
This patch enables SPI DMA transfers for Atmel SAM9 SoCs and implements a bounce buffer for transfers which have vmalloc allocated buffers. Those buffers are not cache coherent even if they have been transformed into sg lists. UBIFS is affected by this cache coherency issue. In this patch I also reverted "spi: atmel: fix corrupted data issue on SAM9 family SoCs"(7094576ccdc3acfe1e06a1e2ab547add375baf7f). Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-19spi: atmel: fixed spin_lock usage inside atmel_spi_removeRadu Pirea
The only part of atmel_spi_remove which needs to be atomic is hardware reset. atmel_spi_stop_dma calls dma_terminate_all and this needs interrupts enabled. atmel_spi_release_dma calls dma_release_channel and dma_release_channel locks a mutex inside of spin_lock. So the call of these functions can't be inside a spin_lock. Reported-by: Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-07-03Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/bcm63xx', ↵Mark Brown
'spi/topic/davinci' and 'spi/topic/imx' into spi-next
2017-06-23spi: atmel: fix corrupted data issue on SAM9 family SoCsCyrille Pitchen
This patch disables the use of the DMA for data transfer and forces the use of PIO transfers instead as a quick fixup to solve the cache aliasing issue on ARM9 based cores, which embeds a VIVT data cache. Indeed in the case of VIVT data caches, it is not safe to call dma_map_*() functions to map buffers for DMA transfers when those buffers have been allocated by vmalloc() or from any DMA-unsafe area. Further patches may propose a better solution based on the use of a bounce buffer at the SPI sub-system level but such solution needs more time to be discussed. Then the use of DMA transfers could be enabled again to improve the performances but before that, this patch already solves the issue. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2017-06-06spi: atmel: print version only after successful registrationBaruch Siach
Don't print the version at the beginning of atmel_spi_probe(). This avoids spamming the log whenever a deferred probe runs. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-18spi: atmel: add deepest PM support to SAMA5D2Quentin Schulz
This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2 SoC's SPI controller. When resuming from deepest state, it is required to restore MR register as the registers are lost since VDD core has been shut down when entering deepest state on the SAMA5D2. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-12spi: atmel: factorize reusable code for SPI controller initQuentin Schulz
The SPI controller configuration during the init can be reused, for the resume function for example. Let's move this configuration to a separate function. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-12Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/ath79', ↵Mark Brown
'spi/topic/atmel' and 'spi/topic/axi' into spi-next
2016-11-25spi: atmel: remove the use of private channel fieldsNicolas Ferre
For DMA transfers, we now use the core DMA framework which provides channel fields in the spi_master structure. Remove the private channels from atmel_spi stucture which were located in a sub-structure. This last one (atmel_spi_dma) which is now empty is also removed. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25spi: atmel: trivial: remove unused fields in DMA structureNicolas Ferre
The atmel_spi_dma structure was cluttered with unused fields relative to older DMA channel selection API. Remove them. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25spi: atmel: Use SPI core DMA mapping frameworkCyrille Pitchen
Use the SPI core DMA mapping framework instead of our own in case of DMA support. PDC support is not converted to this framework. The driver is now able to transfer a complete sg list through DMA. This eventually fix an issue with vmalloc'ed DMA memory that is provided for example by UBI/UBIFS layers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [nicolas.ferre@atmel.com: restrict the use to non-PDC DMA] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25spi: atmel: Use core SPI_MASTER_MUST_[RT]X handlingNicolas Ferre
We need both RX and TX data for each transfer in any case (PIO, PDC, DMA). So convert the driver to the core dummy buffer handling with the SPI_MASTER_MUST_RX/SPI_MASTER_MUST_TX infrastructure. This move changes the maximum PDC/DMA buffer handling to 65535 bytes instead of a single page and sets master->max_dma_len to this value. All dummy buffer management is removed from the driver. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-25spi: atmel: trivial: move info banner to latest probe actionNicolas Ferre
The info banner is here to tell that everything went well, so place it at the very end of the probe function. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-15spi: atmel: Fix scheduling while atomicBen Whitten
A call to clk_get_rate appears to be called in the context of an interrupt, cache the bus clock for the frequency calculations in transmission. This fixes a 'BUG: scheduling while atomic' and 'WARNING: CPU: 0 PID: 777 at kernel/sched/core.c:2960 atmel_spi_unlock' Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Steve deRosier <steve.derosier@lairdtech.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-14spi: atmel: fix indenting in atmel_spi_gpio_cs()Dan Carpenter
These lines were indented one extra tab. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-09spi: atmel: use managed resource for gpio chip selectNicolas Ferre
Use the managed gpio CS pin request so that we avoid having trouble in the cleanup code. In fact, if module was configured with DT, cleanup code released invalid pin. Since resource wasn't freed, module cannot be reinserted. This require to extract the gpio request call from the "setup" function and call it in the appropriate probe function. Reported-by: Alexander Morozov <linux@meltdown.ru> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-28spi: atmel: fix gpio chip-select in case of non-DT platformCyrille Pitchen
The non-DT platform that uses this driver (actually the AVR32) was taking a bad branch for determining if the IP would use gpio for CS. Adding the presence of DT as a condition fixes this issue. Fixes: 4820303480a1 ("spi: atmel: add support for the internal chip-select of the spi controller") Reported-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [nicolas.ferre@atmel.com: extract from ml discussion] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2015-11-04Merge remote-tracking branches 'spi/topic/ath97', 'spi/topic/atmel', ↵Mark Brown
'spi/topic/au1550', 'spi/topic/bcm2835' and 'spi/topic/bcm2835aux' into spi-next
2015-11-04Merge remote-tracking branches 'spi/fix/atmel', 'spi/fix/imx', ↵Mark Brown
'spi/fix/omap2-mcspi', 'spi/fix/ti-qspi' and 'spi/fix/xilinx' into spi-linus
2015-10-23spi: atmel: Fix DMA-setup for transfers with more than 8 bits per wordDavid Mosberger-Tang
The DMA-slave configuration depends on the whether <= 8 or > 8 bits are transferred per word, so we need to call atmel_spi_dma_slave_config() with the correct value. Signed-off-by: David Mosberger <davidm@egauge.net> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2015-09-25spi: atmel: Remove needless bits_per_word and speed_hz testsJarkko Nikula
SPI core validates both bits_per_word and speed_hz transfer parameters and defaults to spi->bits_per_word and spi->max_speed_hz in case these per transfer parameters are not set. This makes possible to remove two if statements and remove one code block that is never executed. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-09-22Merge remote-tracking branches 'spi/fix/atmel', 'spi/fix/bcm2835', ↵Mark Brown
'spi/fix/doc', 'spi/fix/mediatek', 'spi/fix/meson', 'spi/fix/mtk' and 'spi/fix/pxa2xx' into spi-linus
2015-09-10spi: atmel: remove warning when !CONFIG_PM_SLEEPAlexandre Belloni
When CONFIG_PM is defined but not CONFIG_PM_SLEEP (this happens when CONFIG_SUSPEND is not defined), there is the following warning: drivers/spi/spi-atmel.c:1723:12: warning: ‘atmel_spi_suspend’ defined but not used [-Wunused-function] drivers/spi/spi-atmel.c:1741:12: warning: ‘atmel_spi_resume’ defined but not used [-Wunused-function] Enclose both atmel_spi_suspend and atmel_spi_resume in #ifdef CONFIG_PM_SLEEP/#endif to solve that. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-10spi: atmel: remove useless includeAlexandre Belloni
Definitions from linux/platform_data/atmel.h are not used, remove the include. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16spi: atmel: add support to FIFOsCyrille Pitchen
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs. When FIFOs are enabled, they can either work in SINGLE data mode or MULTIPLE data mode. The selected mode depends on the configuration of the SPI controller (see below). In SINGLE data mode (or legacy mode), for a single I/O access, only one data can be read from the Receive Data Register (RDR) or written into the Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up to 4 data can be read from the RDR or up 2 data can be written into the TDR in a single 32bit I/O access. So programmers should take good care of the width of the I/O access to read/write the right number of data. The exact number of read/written data depends on both the I/O access width and the data width (from 8 up to 16 bits). To enable the FIFO feature a "atmel,fifo-size" property must be set to provide the maximum number of data (not bytes) the RX and TX FIFOs can store. Hence a 32 data FIFO can always store up to 32 data unrelated with the actual data width. When FIFOs are enabled, the RX one is forced to operate in SINGLE data mode because this driver configures the spi controller as a master. In master mode only, the Received Data Register has an additionnal Peripheral Chip Select field, which prevents us from reading more than a single data at each register access. Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a 8bit data size is used, only two data by access could be written into the Transmit Data Register. Indeed the first data has to be written into the lowest 16 bits whereas the second data has to be written into the highest 16 bits of the TDR. When DMA transfers are used to send data, we don't rework the transmit buffer to cope with this hardware limitation: the additional copies required to prepare a new input buffer suited to both the DMA controller and the spi controller would waste all the benefit of the DMA transfer. Instead, the DMA controller is configured to write only one data at time into the TDR. In pio mode, two data are written in the TDR in a single access. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-09spi: atmel: add support for the internal chip-select of the spi controllerCyrille Pitchen
This patch relies on the CSAAT (Chip Select Active After Transfer) feature introduced by the version 2 of the spi controller. This new mode allows to use properly the internal chip-select output pin of the spi controller instead of using external gpios. Consequently, the "cs-gpios" device-tree property becomes optional. When the new CSAAT bit is set into the Chip Select Register, the internal chip-select output pin remains asserted till both the following conditions become true: - the LASTXFER bit is set into the Control Register (or the Transmit Data Register) - the Transmit Data Register and its shift register are empty. WARNING: if the LASTXFER bit is set into the Control Register then new data are written into the Transmit Data Register fast enough to keep its shifter not empty, the chip-select output pin remains asserted. Only when the shifter becomes empty, the chip-select output pin is unasserted. When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit is ignored in both the Control Register and the Transmit Data Register. The internal chip-select output pin remains active as long as the Transmit Data Register or its shift register are not empty. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-11Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/bcm2385', ↵Mark Brown
'spi/topic/bcm2835', 'spi/topic/bcm53xx' and 'spi/topic/bitbang' into spi-next
2015-03-22spi: atmel: use endian agnostic IOBen Dooks
Use the endian agnositc IO functions instead of the __raw ones for when the driver is in use on big-endian systems. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-02-26spi: atmel: Fix interrupt setup for PDC transfersTorsten Fleischer
Additionally to the current DMA transfer the PDC allows to set up a next DMA transfer. This is useful for larger SPI transfers. The driver currently waits for ENDRX as end of the transfer. But ENDRX is set when the current DMA transfer is done (RCR = 0), i.e. it doesn't include the next DMA transfer. Thus a subsequent SPI transfer could be started although there is currently a transfer in progress. This can cause invalid accesses to the SPI slave devices and to SPI transfer errors. This issue has been observed on a hardware with a M25P128 SPI NOR flash. So instead of ENDRX we should wait for RXBUFF. This flag is set if there is no more DMA transfer in progress (RCR = RNCR = 0). Signed-off-by: Torsten Fleischer <torfl6749@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2015-02-04spi: atmel: cleanup wait_for_completion return handlingNicholas Mc Guire
return type of wait_for_completion_timeout is unsigned long not int, this patch adds an appropriate variable and fixes up the assignment. It removes the else branch as the only thing it was doing is assigning ret = 0; - but ret is never used thereafter so that is not needed. As the string in dev_err already states "timeout" there is little point in printing the 0. A typo in "trasfer" -> transfer is also fixed. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>