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path: root/drivers/spi/spi-stm32-qspi.c
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2019-08-02spi: Remove dev_err() usage after platform_get_irq()Stephen Boyd
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-04Merge branch 'spi-5.3' into spi-nextMark Brown
2019-06-28spi: stm32-qspi: remove signal sensitive on completionLudovic Barre
On umount step a sigkill signal is set (without user specific action), due to sigkill signal the completion will be interrupted and the data transfer can't be finished if a sync is needed. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-24spi: spi-stm32-qspi: Remove CR_FTHRES_MASK usagePatrice Chotard
On STM32 F4/F7/H7 SoCs, FTHRES is a 5 bits field in QSPI_CR register, but for STM32MP1 SoCs, FTHRES is a 4 bits field long. CR_FTHRES_MASK definition is not correct. As for all these SoCs, FTHRES field is set to 3, FIELD_PREP() macro is used with a constant as second parameter which make its usage useless. CR_FTHRES_MASK and FIELD_PREP() can be removed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02spi: stm32-qspi: manage the get_irq error caseFabien Dessenne
During probe, check the "get_irq" error value. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-26spi: stm32-qspi: add dma supportLudovic Barre
This patch adds the dma support for the stm32-qspi hardware. The memory buffer constraints (lowmem, vmalloc, kmap) are taken into account by framework. In read mode, the memory map is preferred vs dma (due to better throughput). If the dma transfer fails the buffer is sent by polling. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-26spi: stm32-qspi: add spi_master_put in release functionLudovic Barre
This patch adds spi_master_put in release function to drop the controller's refcount. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-20spi: spi-mem: stm32-qspi: stm32_qspi_pm_ops can be statickbuild test robot
Fixes: 2e541b64ee52 ("spi: spi-mem: stm32-qspi: add suspend/resume support") Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-15spi: spi-mem: stm32-qspi: add suspend/resume supportLudovic Barre
This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-15spi: spi-mem: stm32-qspi: avoid memory corruption at low frequencyLudovic Barre
This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-19spi: spi-mem: add stm32 qspi controllerLudovic Barre
The qspi controller is a specialized communication interface targeting single, dual or quad SPI Flash memories (NOR/NAND). It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory tested on: -NOR: mx66l51235l -NAND: MT29F2G01ABAGD Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>