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AgeCommit message (Expand)Author
2021-02-16Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-ro...Stephen Boyd
2021-02-16Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into c...Stephen Boyd
2021-02-16Merge branch 'clk-unused' into clk-nextStephen Boyd
2021-02-16Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and ...Stephen Boyd
2021-02-14clk: qoriq: use macros to generate pll_maskWasim Khan
2021-02-11clk: BD718x7: Do not depend on parent driver dataMatti Vaittinen
2021-02-11clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen
2021-02-11clk: si570: Skip NVM to RAM recall operation if an optional property is setSaeed Nowshadi
2021-02-11clk: vc5: Add support for optional load capacitanceAdam Ford
2021-02-09clk: at91: Fix the declaration of the clocksTudor Ambarus
2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel
2021-02-09clk: mediatek: mux: Update parent at enable timeLaurent Pinchart
2021-02-09clk: mediatek: mux: Drop unused clock opsLaurent Pinchart
2021-02-08clk: mediatek: Select all the MT8183 clocks by defaultEnric Balletbo i Serra
2021-02-08clk: remove u300 driverArnd Bergmann
2021-02-08clk: remove sirf prima2/atlas driversArnd Bergmann
2021-02-08clk: remove zte zx driverArnd Bergmann
2021-02-08clk: remove tango4 driverArnd Bergmann
2021-02-08clk: xilinx: move xlnx_vcu clock driver from socMichael Tretter
2021-02-08soc: xilinx: vcu: fix alignment to open parenthesisMichael Tretter
2021-02-08soc: xilinx: vcu: fix repeated word the in commentMichael Tretter
2021-02-08soc: xilinx: vcu: use bitfields for register definitionMichael Tretter
2021-02-08soc: xilinx: vcu: remove calculation of PLL configurationMichael Tretter
2021-02-08soc: xilinx: vcu: make the PLL configurableMichael Tretter
2021-02-08soc: xilinx: vcu: make pll post divider explicitMichael Tretter
2021-02-08soc: xilinx: vcu: implement clock provider for output clocksMichael Tretter
2021-02-08soc: xilinx: vcu: register PLL as fixed rate clockMichael Tretter
2021-02-08soc: xilinx: vcu: implement PLL disableMichael Tretter
2021-02-08soc: xilinx: vcu: add helpers for configuring PLLMichael Tretter
2021-02-08soc: xilinx: vcu: add helper to wait for PLL lockedMichael Tretter
2021-02-08soc: xilinx: vcu: drop coreclk from struct xlnx_vcuMichael Tretter
2021-02-08clk: divider: fix initialization with parent_hwMichael Tretter
2021-02-08clk: axi-clkgen: use devm_platform_ioremap_resource() short-handAlexandru Ardelean
2021-02-08clk: clk-axiclkgen: add ZynqMP PFD and VCO limitsAlexandru Ardelean
2021-02-08clk: axi-clkgen: replace ARCH dependencies with driver depsAlexandru Ardelean
2021-02-08clk: Drop unused efm32gg driverUwe Kleine-König
2021-02-06clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner
2021-02-06clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner
2021-02-06clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner
2021-01-30clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible headerLee Jones
2021-01-30clk: imx8mn: add clkout1/2 supportLucas Stach
2021-01-30clk: imx8mm: add clkout1/2 supportLucas Stach
2021-01-30clk: imx8mq: add PLL monitor outputLucas Stach
2021-01-29clk: imx: clk-imx31: Remove unused static const table 'uart_clks'Lee Jones
2021-01-29clk: imx6q: demote warning about pre-boot ldb_di_clk reparentingAhmad Fatoum
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 CCUAndre Przywara
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 R-CCUAndre Przywara
2021-01-28clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentationLee Jones
2021-01-26clk: rockchip: Demote non-conformant kernel-doc header in half-dividerLee Jones
2021-01-26clk: rockchip: Demote kernel-doc abuses to standard comment blocks in pllsLee Jones